pseudo_inst.cc (9952:7437cc334df1) pseudo_inst.cc (10553:c1ad57c53a36)
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2011 Advanced Micro Devices, Inc.
15 * Copyright (c) 2003-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Nathan Binkert
42 */
43
44#include <fcntl.h>
45#include <unistd.h>
46
47#include <cerrno>
48#include <fstream>
49#include <string>
50#include <vector>
51
52#include "arch/kernel_stats.hh"
53#include "arch/utility.hh"
54#include "arch/vtophys.hh"
1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2011 Advanced Micro Devices, Inc.
15 * Copyright (c) 2003-2006 The Regents of The University of Michigan
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 *
41 * Authors: Nathan Binkert
42 */
43
44#include <fcntl.h>
45#include <unistd.h>
46
47#include <cerrno>
48#include <fstream>
49#include <string>
50#include <vector>
51
52#include "arch/kernel_stats.hh"
53#include "arch/utility.hh"
54#include "arch/vtophys.hh"
55#include "arch/pseudo_inst.hh"
55#include "base/debug.hh"
56#include "base/output.hh"
57#include "config/the_isa.hh"
58#include "cpu/base.hh"
59#include "cpu/quiesce_event.hh"
60#include "cpu/thread_context.hh"
61#include "debug/Loader.hh"
62#include "debug/PseudoInst.hh"
63#include "debug/Quiesce.hh"
64#include "debug/WorkItems.hh"
65#include "params/BaseCPU.hh"
66#include "sim/full_system.hh"
56#include "base/debug.hh"
57#include "base/output.hh"
58#include "config/the_isa.hh"
59#include "cpu/base.hh"
60#include "cpu/quiesce_event.hh"
61#include "cpu/thread_context.hh"
62#include "debug/Loader.hh"
63#include "debug/PseudoInst.hh"
64#include "debug/Quiesce.hh"
65#include "debug/WorkItems.hh"
66#include "params/BaseCPU.hh"
67#include "sim/full_system.hh"
68#include "sim/process.hh"
67#include "sim/pseudo_inst.hh"
68#include "sim/serialize.hh"
69#include "sim/sim_events.hh"
70#include "sim/sim_exit.hh"
71#include "sim/stat_control.hh"
72#include "sim/stats.hh"
73#include "sim/system.hh"
74#include "sim/vptr.hh"
75
76using namespace std;
77
78using namespace Stats;
79using namespace TheISA;
80
81namespace PseudoInst {
82
83static inline void
84panicFsOnlyPseudoInst(const char *name)
85{
86 panic("Pseudo inst \"%s\" is only available in Full System mode.");
87}
88
89uint64_t
90pseudoInst(ThreadContext *tc, uint8_t func, uint8_t subfunc)
91{
92 uint64_t args[4];
93
94 DPRINTF(PseudoInst, "PseudoInst::pseudoInst(%i, %i)\n", func, subfunc);
95
96 // We need to do this in a slightly convoluted way since
97 // getArgument() might have side-effects on arg_num. We could have
98 // used the Argument class, but due to the possible side effects
99 // from getArgument, it'd most likely break.
100 int arg_num(0);
101 for (int i = 0; i < sizeof(args) / sizeof(*args); ++i) {
102 args[arg_num] = getArgument(tc, arg_num, sizeof(uint64_t), false);
103 ++arg_num;
104 }
105
106 switch (func) {
107 case 0x00: // arm_func
108 arm(tc);
109 break;
110
111 case 0x01: // quiesce_func
112 quiesce(tc);
113 break;
114
115 case 0x02: // quiescens_func
116 quiesceSkip(tc);
117 break;
118
119 case 0x03: // quiescecycle_func
120 quiesceNs(tc, args[0]);
121 break;
122
123 case 0x04: // quiescetime_func
124 return quiesceTime(tc);
125
126 case 0x07: // rpns_func
127 return rpns(tc);
128
129 case 0x09: // wakecpu_func
130 wakeCPU(tc, args[0]);
131 break;
132
133 case 0x21: // exit_func
134 m5exit(tc, args[0]);
135 break;
136
137 case 0x22:
138 m5fail(tc, args[0], args[1]);
139 break;
140
141 case 0x30: // initparam_func
142 return initParam(tc);
143
144 case 0x31: // loadsymbol_func
145 loadsymbol(tc);
146 break;
147
148 case 0x40: // resetstats_func
149 resetstats(tc, args[0], args[1]);
150 break;
151
152 case 0x41: // dumpstats_func
153 dumpstats(tc, args[0], args[1]);
154 break;
155
156 case 0x42: // dumprststats_func
157 dumpresetstats(tc, args[0], args[1]);
158 break;
159
160 case 0x43: // ckpt_func
161 m5checkpoint(tc, args[0], args[1]);
162 break;
163
164 case 0x4f: // writefile_func
165 return writefile(tc, args[0], args[1], args[2], args[3]);
166
167 case 0x50: // readfile_func
168 return readfile(tc, args[0], args[1], args[2]);
169
170 case 0x51: // debugbreak_func
171 debugbreak(tc);
172 break;
173
174 case 0x52: // switchcpu_func
175 switchcpu(tc);
176 break;
177
178 case 0x53: // addsymbol_func
179 addsymbol(tc, args[0], args[1]);
180 break;
181
182 case 0x54: // panic_func
183 panic("M5 panic instruction called at %s\n", tc->pcState());
184
185 case 0x5a: // work_begin_func
186 workbegin(tc, args[0], args[1]);
187 break;
188
189 case 0x5b: // work_end_func
190 workend(tc, args[0], args[1]);
191 break;
192
193 case 0x55: // annotate_func
194 case 0x56: // reserved2_func
195 case 0x57: // reserved3_func
196 case 0x58: // reserved4_func
197 case 0x59: // reserved5_func
198 warn("Unimplemented m5 op (0x%x)\n", func);
199 break;
200
69#include "sim/pseudo_inst.hh"
70#include "sim/serialize.hh"
71#include "sim/sim_events.hh"
72#include "sim/sim_exit.hh"
73#include "sim/stat_control.hh"
74#include "sim/stats.hh"
75#include "sim/system.hh"
76#include "sim/vptr.hh"
77
78using namespace std;
79
80using namespace Stats;
81using namespace TheISA;
82
83namespace PseudoInst {
84
85static inline void
86panicFsOnlyPseudoInst(const char *name)
87{
88 panic("Pseudo inst \"%s\" is only available in Full System mode.");
89}
90
91uint64_t
92pseudoInst(ThreadContext *tc, uint8_t func, uint8_t subfunc)
93{
94 uint64_t args[4];
95
96 DPRINTF(PseudoInst, "PseudoInst::pseudoInst(%i, %i)\n", func, subfunc);
97
98 // We need to do this in a slightly convoluted way since
99 // getArgument() might have side-effects on arg_num. We could have
100 // used the Argument class, but due to the possible side effects
101 // from getArgument, it'd most likely break.
102 int arg_num(0);
103 for (int i = 0; i < sizeof(args) / sizeof(*args); ++i) {
104 args[arg_num] = getArgument(tc, arg_num, sizeof(uint64_t), false);
105 ++arg_num;
106 }
107
108 switch (func) {
109 case 0x00: // arm_func
110 arm(tc);
111 break;
112
113 case 0x01: // quiesce_func
114 quiesce(tc);
115 break;
116
117 case 0x02: // quiescens_func
118 quiesceSkip(tc);
119 break;
120
121 case 0x03: // quiescecycle_func
122 quiesceNs(tc, args[0]);
123 break;
124
125 case 0x04: // quiescetime_func
126 return quiesceTime(tc);
127
128 case 0x07: // rpns_func
129 return rpns(tc);
130
131 case 0x09: // wakecpu_func
132 wakeCPU(tc, args[0]);
133 break;
134
135 case 0x21: // exit_func
136 m5exit(tc, args[0]);
137 break;
138
139 case 0x22:
140 m5fail(tc, args[0], args[1]);
141 break;
142
143 case 0x30: // initparam_func
144 return initParam(tc);
145
146 case 0x31: // loadsymbol_func
147 loadsymbol(tc);
148 break;
149
150 case 0x40: // resetstats_func
151 resetstats(tc, args[0], args[1]);
152 break;
153
154 case 0x41: // dumpstats_func
155 dumpstats(tc, args[0], args[1]);
156 break;
157
158 case 0x42: // dumprststats_func
159 dumpresetstats(tc, args[0], args[1]);
160 break;
161
162 case 0x43: // ckpt_func
163 m5checkpoint(tc, args[0], args[1]);
164 break;
165
166 case 0x4f: // writefile_func
167 return writefile(tc, args[0], args[1], args[2], args[3]);
168
169 case 0x50: // readfile_func
170 return readfile(tc, args[0], args[1], args[2]);
171
172 case 0x51: // debugbreak_func
173 debugbreak(tc);
174 break;
175
176 case 0x52: // switchcpu_func
177 switchcpu(tc);
178 break;
179
180 case 0x53: // addsymbol_func
181 addsymbol(tc, args[0], args[1]);
182 break;
183
184 case 0x54: // panic_func
185 panic("M5 panic instruction called at %s\n", tc->pcState());
186
187 case 0x5a: // work_begin_func
188 workbegin(tc, args[0], args[1]);
189 break;
190
191 case 0x5b: // work_end_func
192 workend(tc, args[0], args[1]);
193 break;
194
195 case 0x55: // annotate_func
196 case 0x56: // reserved2_func
197 case 0x57: // reserved3_func
198 case 0x58: // reserved4_func
199 case 0x59: // reserved5_func
200 warn("Unimplemented m5 op (0x%x)\n", func);
201 break;
202
203 /* SE mode functions */
204 case 0x60: // syscall_func
205 m5Syscall(tc);
206 break;
207
208 case 0x61: // pagefault_func
209 m5PageFault(tc);
210 break;
211
201 default:
202 warn("Unhandled m5 op: 0x%x\n", func);
203 break;
204 }
205
206 return 0;
207}
208
209void
210arm(ThreadContext *tc)
211{
212 DPRINTF(PseudoInst, "PseudoInst::arm()\n");
213 if (!FullSystem)
214 panicFsOnlyPseudoInst("arm");
215
216 if (tc->getKernelStats())
217 tc->getKernelStats()->arm();
218}
219
220void
221quiesce(ThreadContext *tc)
222{
223 DPRINTF(PseudoInst, "PseudoInst::quiesce()\n");
224 if (!FullSystem)
225 panicFsOnlyPseudoInst("quiesce");
226
227 if (!tc->getCpuPtr()->params()->do_quiesce)
228 return;
229
230 DPRINTF(Quiesce, "%s: quiesce()\n", tc->getCpuPtr()->name());
231
232 tc->suspend();
233 if (tc->getKernelStats())
234 tc->getKernelStats()->quiesce();
235}
236
237void
238quiesceSkip(ThreadContext *tc)
239{
240 DPRINTF(PseudoInst, "PseudoInst::quiesceSkip()\n");
241 if (!FullSystem)
242 panicFsOnlyPseudoInst("quiesceSkip");
243
244 BaseCPU *cpu = tc->getCpuPtr();
245
246 if (!cpu->params()->do_quiesce)
247 return;
248
249 EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
250
251 Tick resume = curTick() + 1;
252
253 cpu->reschedule(quiesceEvent, resume, true);
254
255 DPRINTF(Quiesce, "%s: quiesceSkip() until %d\n",
256 cpu->name(), resume);
257
258 tc->suspend();
259 if (tc->getKernelStats())
260 tc->getKernelStats()->quiesce();
261}
262
263void
264quiesceNs(ThreadContext *tc, uint64_t ns)
265{
266 DPRINTF(PseudoInst, "PseudoInst::quiesceNs(%i)\n", ns);
267 if (!FullSystem)
268 panicFsOnlyPseudoInst("quiesceNs");
269
270 BaseCPU *cpu = tc->getCpuPtr();
271
272 if (!cpu->params()->do_quiesce || ns == 0)
273 return;
274
275 EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
276
277 Tick resume = curTick() + SimClock::Int::ns * ns;
278
279 cpu->reschedule(quiesceEvent, resume, true);
280
281 DPRINTF(Quiesce, "%s: quiesceNs(%d) until %d\n",
282 cpu->name(), ns, resume);
283
284 tc->suspend();
285 if (tc->getKernelStats())
286 tc->getKernelStats()->quiesce();
287}
288
289void
290quiesceCycles(ThreadContext *tc, uint64_t cycles)
291{
292 DPRINTF(PseudoInst, "PseudoInst::quiesceCycles(%i)\n", cycles);
293 if (!FullSystem)
294 panicFsOnlyPseudoInst("quiesceCycles");
295
296 BaseCPU *cpu = tc->getCpuPtr();
297
298 if (!cpu->params()->do_quiesce || cycles == 0)
299 return;
300
301 EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
302
303 Tick resume = cpu->clockEdge(Cycles(cycles));
304
305 cpu->reschedule(quiesceEvent, resume, true);
306
307 DPRINTF(Quiesce, "%s: quiesceCycles(%d) until %d\n",
308 cpu->name(), cycles, resume);
309
310 tc->suspend();
311 if (tc->getKernelStats())
312 tc->getKernelStats()->quiesce();
313}
314
315uint64_t
316quiesceTime(ThreadContext *tc)
317{
318 DPRINTF(PseudoInst, "PseudoInst::quiesceTime()\n");
319 if (!FullSystem) {
320 panicFsOnlyPseudoInst("quiesceTime");
321 return 0;
322 }
323
324 return (tc->readLastActivate() - tc->readLastSuspend()) /
325 SimClock::Int::ns;
326}
327
328uint64_t
329rpns(ThreadContext *tc)
330{
331 DPRINTF(PseudoInst, "PseudoInst::rpns()\n");
332 return curTick() / SimClock::Int::ns;
333}
334
335void
336wakeCPU(ThreadContext *tc, uint64_t cpuid)
337{
338 DPRINTF(PseudoInst, "PseudoInst::wakeCPU(%i)\n", cpuid);
339 System *sys = tc->getSystemPtr();
340 ThreadContext *other_tc = sys->threadContexts[cpuid];
341 if (other_tc->status() == ThreadContext::Suspended)
342 other_tc->activate();
343}
344
345void
346m5exit(ThreadContext *tc, Tick delay)
347{
348 DPRINTF(PseudoInst, "PseudoInst::m5exit(%i)\n", delay);
349 Tick when = curTick() + delay * SimClock::Int::ns;
350 exitSimLoop("m5_exit instruction encountered", 0, when, 0, true);
351}
352
353void
354m5fail(ThreadContext *tc, Tick delay, uint64_t code)
355{
356 DPRINTF(PseudoInst, "PseudoInst::m5fail(%i, %i)\n", delay, code);
357 Tick when = curTick() + delay * SimClock::Int::ns;
358 exitSimLoop("m5_fail instruction encountered", code, when, 0, true);
359}
360
361void
362loadsymbol(ThreadContext *tc)
363{
364 DPRINTF(PseudoInst, "PseudoInst::loadsymbol()\n");
365 if (!FullSystem)
366 panicFsOnlyPseudoInst("loadsymbol");
367
368 const string &filename = tc->getCpuPtr()->system->params()->symbolfile;
369 if (filename.empty()) {
370 return;
371 }
372
373 std::string buffer;
374 ifstream file(filename.c_str());
375
376 if (!file)
377 fatal("file error: Can't open symbol table file %s\n", filename);
378
379 while (!file.eof()) {
380 getline(file, buffer);
381
382 if (buffer.empty())
383 continue;
384
385 string::size_type idx = buffer.find(' ');
386 if (idx == string::npos)
387 continue;
388
389 string address = "0x" + buffer.substr(0, idx);
390 eat_white(address);
391 if (address.empty())
392 continue;
393
394 // Skip over letter and space
395 string symbol = buffer.substr(idx + 3);
396 eat_white(symbol);
397 if (symbol.empty())
398 continue;
399
400 Addr addr;
401 if (!to_number(address, addr))
402 continue;
403
404 if (!tc->getSystemPtr()->kernelSymtab->insert(addr, symbol))
405 continue;
406
407
408 DPRINTF(Loader, "Loaded symbol: %s @ %#llx\n", symbol, addr);
409 }
410 file.close();
411}
412
413void
414addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr)
415{
416 DPRINTF(PseudoInst, "PseudoInst::addsymbol(0x%x, 0x%x)\n",
417 addr, symbolAddr);
418 if (!FullSystem)
419 panicFsOnlyPseudoInst("addSymbol");
420
421 char symb[100];
422 CopyStringOut(tc, symb, symbolAddr, 100);
423 std::string symbol(symb);
424
425 DPRINTF(Loader, "Loaded symbol: %s @ %#llx\n", symbol, addr);
426
427 tc->getSystemPtr()->kernelSymtab->insert(addr,symbol);
428 debugSymbolTable->insert(addr,symbol);
429}
430
431uint64_t
432initParam(ThreadContext *tc)
433{
434 DPRINTF(PseudoInst, "PseudoInst::initParam()\n");
435 if (!FullSystem) {
436 panicFsOnlyPseudoInst("initParam");
437 return 0;
438 }
439
440 return tc->getCpuPtr()->system->init_param;
441}
442
443
444void
445resetstats(ThreadContext *tc, Tick delay, Tick period)
446{
447 DPRINTF(PseudoInst, "PseudoInst::resetstats(%i, %i)\n", delay, period);
448 if (!tc->getCpuPtr()->params()->do_statistics_insts)
449 return;
450
451
452 Tick when = curTick() + delay * SimClock::Int::ns;
453 Tick repeat = period * SimClock::Int::ns;
454
455 Stats::schedStatEvent(false, true, when, repeat);
456}
457
458void
459dumpstats(ThreadContext *tc, Tick delay, Tick period)
460{
461 DPRINTF(PseudoInst, "PseudoInst::dumpstats(%i, %i)\n", delay, period);
462 if (!tc->getCpuPtr()->params()->do_statistics_insts)
463 return;
464
465
466 Tick when = curTick() + delay * SimClock::Int::ns;
467 Tick repeat = period * SimClock::Int::ns;
468
469 Stats::schedStatEvent(true, false, when, repeat);
470}
471
472void
473dumpresetstats(ThreadContext *tc, Tick delay, Tick period)
474{
475 DPRINTF(PseudoInst, "PseudoInst::dumpresetstats(%i, %i)\n", delay, period);
476 if (!tc->getCpuPtr()->params()->do_statistics_insts)
477 return;
478
479
480 Tick when = curTick() + delay * SimClock::Int::ns;
481 Tick repeat = period * SimClock::Int::ns;
482
483 Stats::schedStatEvent(true, true, when, repeat);
484}
485
486void
487m5checkpoint(ThreadContext *tc, Tick delay, Tick period)
488{
489 DPRINTF(PseudoInst, "PseudoInst::m5checkpoint(%i, %i)\n", delay, period);
490 if (!tc->getCpuPtr()->params()->do_checkpoint_insts)
491 return;
492
493 Tick when = curTick() + delay * SimClock::Int::ns;
494 Tick repeat = period * SimClock::Int::ns;
495
496 exitSimLoop("checkpoint", 0, when, repeat);
497}
498
499uint64_t
500readfile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset)
501{
502 DPRINTF(PseudoInst, "PseudoInst::readfile(0x%x, 0x%x, 0x%x)\n",
503 vaddr, len, offset);
504 if (!FullSystem) {
505 panicFsOnlyPseudoInst("readfile");
506 return 0;
507 }
508
509 const string &file = tc->getSystemPtr()->params()->readfile;
510 if (file.empty()) {
511 return ULL(0);
512 }
513
514 uint64_t result = 0;
515
516 int fd = ::open(file.c_str(), O_RDONLY, 0);
517 if (fd < 0)
518 panic("could not open file %s\n", file);
519
520 if (::lseek(fd, offset, SEEK_SET) < 0)
521 panic("could not seek: %s", strerror(errno));
522
523 char *buf = new char[len];
524 char *p = buf;
525 while (len > 0) {
526 int bytes = ::read(fd, p, len);
527 if (bytes <= 0)
528 break;
529
530 p += bytes;
531 result += bytes;
532 len -= bytes;
533 }
534
535 close(fd);
536 CopyIn(tc, vaddr, buf, result);
537 delete [] buf;
538 return result;
539}
540
541uint64_t
542writefile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset,
543 Addr filename_addr)
544{
545 DPRINTF(PseudoInst, "PseudoInst::writefile(0x%x, 0x%x, 0x%x, 0x%x)\n",
546 vaddr, len, offset, filename_addr);
547 ostream *os;
548
549 // copy out target filename
550 char fn[100];
551 std::string filename;
552 CopyStringOut(tc, fn, filename_addr, 100);
553 filename = std::string(fn);
554
555 if (offset == 0) {
556 // create a new file (truncate)
557 os = simout.create(filename, true);
558 } else {
559 // do not truncate file if offset is non-zero
560 // (ios::in flag is required as well to keep the existing data
561 // intact, otherwise existing data will be zeroed out.)
562 os = simout.openFile(simout.directory() + filename,
563 ios::in | ios::out | ios::binary);
564 }
565 if (!os)
566 panic("could not open file %s\n", filename);
567
568 // seek to offset
569 os->seekp(offset);
570
571 // copy out data and write to file
572 char *buf = new char[len];
573 CopyOut(tc, buf, vaddr, len);
574 os->write(buf, len);
575 if (os->fail() || os->bad())
576 panic("Error while doing writefile!\n");
577
578 simout.close(os);
579
580 delete [] buf;
581
582 return len;
583}
584
585void
586debugbreak(ThreadContext *tc)
587{
588 DPRINTF(PseudoInst, "PseudoInst::debugbreak()\n");
589 Debug::breakpoint();
590}
591
592void
593switchcpu(ThreadContext *tc)
594{
595 DPRINTF(PseudoInst, "PseudoInst::switchcpu()\n");
596 exitSimLoop("switchcpu");
597}
598
599//
600// This function is executed when annotated work items begin. Depending on
601// what the user specified at the command line, the simulation may exit and/or
602// take a checkpoint when a certain work item begins.
603//
604void
605workbegin(ThreadContext *tc, uint64_t workid, uint64_t threadid)
606{
607 DPRINTF(PseudoInst, "PseudoInst::workbegin(%i, %i)\n", workid, threadid);
608 tc->getCpuPtr()->workItemBegin();
609 System *sys = tc->getSystemPtr();
610 const System::Params *params = sys->params();
611 sys->workItemBegin(threadid, workid);
612
613 DPRINTF(WorkItems, "Work Begin workid: %d, threadid %d\n", workid,
614 threadid);
615
616 //
617 // If specified, determine if this is the specific work item the user
618 // identified
619 //
620 if (params->work_item_id == -1 || params->work_item_id == workid) {
621
622 uint64_t systemWorkBeginCount = sys->incWorkItemsBegin();
623 int cpuId = tc->getCpuPtr()->cpuId();
624
625 if (params->work_cpus_ckpt_count != 0 &&
626 sys->markWorkItem(cpuId) >= params->work_cpus_ckpt_count) {
627 //
628 // If active cpus equals checkpoint count, create checkpoint
629 //
630 exitSimLoop("checkpoint");
631 }
632
633 if (systemWorkBeginCount == params->work_begin_ckpt_count) {
634 //
635 // Note: the string specified as the cause of the exit event must
636 // exactly equal "checkpoint" inorder to create a checkpoint
637 //
638 exitSimLoop("checkpoint");
639 }
640
641 if (systemWorkBeginCount == params->work_begin_exit_count) {
642 //
643 // If a certain number of work items started, exit simulation
644 //
645 exitSimLoop("work started count reach");
646 }
647
648 if (cpuId == params->work_begin_cpu_id_exit) {
649 //
650 // If work started on the cpu id specified, exit simulation
651 //
652 exitSimLoop("work started on specific cpu");
653 }
654 }
655}
656
657//
658// This function is executed when annotated work items end. Depending on
659// what the user specified at the command line, the simulation may exit and/or
660// take a checkpoint when a certain work item ends.
661//
662void
663workend(ThreadContext *tc, uint64_t workid, uint64_t threadid)
664{
665 DPRINTF(PseudoInst, "PseudoInst::workend(%i, %i)\n", workid, threadid);
666 tc->getCpuPtr()->workItemEnd();
667 System *sys = tc->getSystemPtr();
668 const System::Params *params = sys->params();
669 sys->workItemEnd(threadid, workid);
670
671 DPRINTF(WorkItems, "Work End workid: %d, threadid %d\n", workid, threadid);
672
673 //
674 // If specified, determine if this is the specific work item the user
675 // identified
676 //
677 if (params->work_item_id == -1 || params->work_item_id == workid) {
678
679 uint64_t systemWorkEndCount = sys->incWorkItemsEnd();
680 int cpuId = tc->getCpuPtr()->cpuId();
681
682 if (params->work_cpus_ckpt_count != 0 &&
683 sys->markWorkItem(cpuId) >= params->work_cpus_ckpt_count) {
684 //
685 // If active cpus equals checkpoint count, create checkpoint
686 //
687 exitSimLoop("checkpoint");
688 }
689
690 if (params->work_end_ckpt_count != 0 &&
691 systemWorkEndCount == params->work_end_ckpt_count) {
692 //
693 // If total work items completed equals checkpoint count, create
694 // checkpoint
695 //
696 exitSimLoop("checkpoint");
697 }
698
699 if (params->work_end_exit_count != 0 &&
700 systemWorkEndCount == params->work_end_exit_count) {
701 //
702 // If total work items completed equals exit count, exit simulation
703 //
704 exitSimLoop("work items exit count reached");
705 }
706 }
707}
708
709} // namespace PseudoInst
212 default:
213 warn("Unhandled m5 op: 0x%x\n", func);
214 break;
215 }
216
217 return 0;
218}
219
220void
221arm(ThreadContext *tc)
222{
223 DPRINTF(PseudoInst, "PseudoInst::arm()\n");
224 if (!FullSystem)
225 panicFsOnlyPseudoInst("arm");
226
227 if (tc->getKernelStats())
228 tc->getKernelStats()->arm();
229}
230
231void
232quiesce(ThreadContext *tc)
233{
234 DPRINTF(PseudoInst, "PseudoInst::quiesce()\n");
235 if (!FullSystem)
236 panicFsOnlyPseudoInst("quiesce");
237
238 if (!tc->getCpuPtr()->params()->do_quiesce)
239 return;
240
241 DPRINTF(Quiesce, "%s: quiesce()\n", tc->getCpuPtr()->name());
242
243 tc->suspend();
244 if (tc->getKernelStats())
245 tc->getKernelStats()->quiesce();
246}
247
248void
249quiesceSkip(ThreadContext *tc)
250{
251 DPRINTF(PseudoInst, "PseudoInst::quiesceSkip()\n");
252 if (!FullSystem)
253 panicFsOnlyPseudoInst("quiesceSkip");
254
255 BaseCPU *cpu = tc->getCpuPtr();
256
257 if (!cpu->params()->do_quiesce)
258 return;
259
260 EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
261
262 Tick resume = curTick() + 1;
263
264 cpu->reschedule(quiesceEvent, resume, true);
265
266 DPRINTF(Quiesce, "%s: quiesceSkip() until %d\n",
267 cpu->name(), resume);
268
269 tc->suspend();
270 if (tc->getKernelStats())
271 tc->getKernelStats()->quiesce();
272}
273
274void
275quiesceNs(ThreadContext *tc, uint64_t ns)
276{
277 DPRINTF(PseudoInst, "PseudoInst::quiesceNs(%i)\n", ns);
278 if (!FullSystem)
279 panicFsOnlyPseudoInst("quiesceNs");
280
281 BaseCPU *cpu = tc->getCpuPtr();
282
283 if (!cpu->params()->do_quiesce || ns == 0)
284 return;
285
286 EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
287
288 Tick resume = curTick() + SimClock::Int::ns * ns;
289
290 cpu->reschedule(quiesceEvent, resume, true);
291
292 DPRINTF(Quiesce, "%s: quiesceNs(%d) until %d\n",
293 cpu->name(), ns, resume);
294
295 tc->suspend();
296 if (tc->getKernelStats())
297 tc->getKernelStats()->quiesce();
298}
299
300void
301quiesceCycles(ThreadContext *tc, uint64_t cycles)
302{
303 DPRINTF(PseudoInst, "PseudoInst::quiesceCycles(%i)\n", cycles);
304 if (!FullSystem)
305 panicFsOnlyPseudoInst("quiesceCycles");
306
307 BaseCPU *cpu = tc->getCpuPtr();
308
309 if (!cpu->params()->do_quiesce || cycles == 0)
310 return;
311
312 EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
313
314 Tick resume = cpu->clockEdge(Cycles(cycles));
315
316 cpu->reschedule(quiesceEvent, resume, true);
317
318 DPRINTF(Quiesce, "%s: quiesceCycles(%d) until %d\n",
319 cpu->name(), cycles, resume);
320
321 tc->suspend();
322 if (tc->getKernelStats())
323 tc->getKernelStats()->quiesce();
324}
325
326uint64_t
327quiesceTime(ThreadContext *tc)
328{
329 DPRINTF(PseudoInst, "PseudoInst::quiesceTime()\n");
330 if (!FullSystem) {
331 panicFsOnlyPseudoInst("quiesceTime");
332 return 0;
333 }
334
335 return (tc->readLastActivate() - tc->readLastSuspend()) /
336 SimClock::Int::ns;
337}
338
339uint64_t
340rpns(ThreadContext *tc)
341{
342 DPRINTF(PseudoInst, "PseudoInst::rpns()\n");
343 return curTick() / SimClock::Int::ns;
344}
345
346void
347wakeCPU(ThreadContext *tc, uint64_t cpuid)
348{
349 DPRINTF(PseudoInst, "PseudoInst::wakeCPU(%i)\n", cpuid);
350 System *sys = tc->getSystemPtr();
351 ThreadContext *other_tc = sys->threadContexts[cpuid];
352 if (other_tc->status() == ThreadContext::Suspended)
353 other_tc->activate();
354}
355
356void
357m5exit(ThreadContext *tc, Tick delay)
358{
359 DPRINTF(PseudoInst, "PseudoInst::m5exit(%i)\n", delay);
360 Tick when = curTick() + delay * SimClock::Int::ns;
361 exitSimLoop("m5_exit instruction encountered", 0, when, 0, true);
362}
363
364void
365m5fail(ThreadContext *tc, Tick delay, uint64_t code)
366{
367 DPRINTF(PseudoInst, "PseudoInst::m5fail(%i, %i)\n", delay, code);
368 Tick when = curTick() + delay * SimClock::Int::ns;
369 exitSimLoop("m5_fail instruction encountered", code, when, 0, true);
370}
371
372void
373loadsymbol(ThreadContext *tc)
374{
375 DPRINTF(PseudoInst, "PseudoInst::loadsymbol()\n");
376 if (!FullSystem)
377 panicFsOnlyPseudoInst("loadsymbol");
378
379 const string &filename = tc->getCpuPtr()->system->params()->symbolfile;
380 if (filename.empty()) {
381 return;
382 }
383
384 std::string buffer;
385 ifstream file(filename.c_str());
386
387 if (!file)
388 fatal("file error: Can't open symbol table file %s\n", filename);
389
390 while (!file.eof()) {
391 getline(file, buffer);
392
393 if (buffer.empty())
394 continue;
395
396 string::size_type idx = buffer.find(' ');
397 if (idx == string::npos)
398 continue;
399
400 string address = "0x" + buffer.substr(0, idx);
401 eat_white(address);
402 if (address.empty())
403 continue;
404
405 // Skip over letter and space
406 string symbol = buffer.substr(idx + 3);
407 eat_white(symbol);
408 if (symbol.empty())
409 continue;
410
411 Addr addr;
412 if (!to_number(address, addr))
413 continue;
414
415 if (!tc->getSystemPtr()->kernelSymtab->insert(addr, symbol))
416 continue;
417
418
419 DPRINTF(Loader, "Loaded symbol: %s @ %#llx\n", symbol, addr);
420 }
421 file.close();
422}
423
424void
425addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr)
426{
427 DPRINTF(PseudoInst, "PseudoInst::addsymbol(0x%x, 0x%x)\n",
428 addr, symbolAddr);
429 if (!FullSystem)
430 panicFsOnlyPseudoInst("addSymbol");
431
432 char symb[100];
433 CopyStringOut(tc, symb, symbolAddr, 100);
434 std::string symbol(symb);
435
436 DPRINTF(Loader, "Loaded symbol: %s @ %#llx\n", symbol, addr);
437
438 tc->getSystemPtr()->kernelSymtab->insert(addr,symbol);
439 debugSymbolTable->insert(addr,symbol);
440}
441
442uint64_t
443initParam(ThreadContext *tc)
444{
445 DPRINTF(PseudoInst, "PseudoInst::initParam()\n");
446 if (!FullSystem) {
447 panicFsOnlyPseudoInst("initParam");
448 return 0;
449 }
450
451 return tc->getCpuPtr()->system->init_param;
452}
453
454
455void
456resetstats(ThreadContext *tc, Tick delay, Tick period)
457{
458 DPRINTF(PseudoInst, "PseudoInst::resetstats(%i, %i)\n", delay, period);
459 if (!tc->getCpuPtr()->params()->do_statistics_insts)
460 return;
461
462
463 Tick when = curTick() + delay * SimClock::Int::ns;
464 Tick repeat = period * SimClock::Int::ns;
465
466 Stats::schedStatEvent(false, true, when, repeat);
467}
468
469void
470dumpstats(ThreadContext *tc, Tick delay, Tick period)
471{
472 DPRINTF(PseudoInst, "PseudoInst::dumpstats(%i, %i)\n", delay, period);
473 if (!tc->getCpuPtr()->params()->do_statistics_insts)
474 return;
475
476
477 Tick when = curTick() + delay * SimClock::Int::ns;
478 Tick repeat = period * SimClock::Int::ns;
479
480 Stats::schedStatEvent(true, false, when, repeat);
481}
482
483void
484dumpresetstats(ThreadContext *tc, Tick delay, Tick period)
485{
486 DPRINTF(PseudoInst, "PseudoInst::dumpresetstats(%i, %i)\n", delay, period);
487 if (!tc->getCpuPtr()->params()->do_statistics_insts)
488 return;
489
490
491 Tick when = curTick() + delay * SimClock::Int::ns;
492 Tick repeat = period * SimClock::Int::ns;
493
494 Stats::schedStatEvent(true, true, when, repeat);
495}
496
497void
498m5checkpoint(ThreadContext *tc, Tick delay, Tick period)
499{
500 DPRINTF(PseudoInst, "PseudoInst::m5checkpoint(%i, %i)\n", delay, period);
501 if (!tc->getCpuPtr()->params()->do_checkpoint_insts)
502 return;
503
504 Tick when = curTick() + delay * SimClock::Int::ns;
505 Tick repeat = period * SimClock::Int::ns;
506
507 exitSimLoop("checkpoint", 0, when, repeat);
508}
509
510uint64_t
511readfile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset)
512{
513 DPRINTF(PseudoInst, "PseudoInst::readfile(0x%x, 0x%x, 0x%x)\n",
514 vaddr, len, offset);
515 if (!FullSystem) {
516 panicFsOnlyPseudoInst("readfile");
517 return 0;
518 }
519
520 const string &file = tc->getSystemPtr()->params()->readfile;
521 if (file.empty()) {
522 return ULL(0);
523 }
524
525 uint64_t result = 0;
526
527 int fd = ::open(file.c_str(), O_RDONLY, 0);
528 if (fd < 0)
529 panic("could not open file %s\n", file);
530
531 if (::lseek(fd, offset, SEEK_SET) < 0)
532 panic("could not seek: %s", strerror(errno));
533
534 char *buf = new char[len];
535 char *p = buf;
536 while (len > 0) {
537 int bytes = ::read(fd, p, len);
538 if (bytes <= 0)
539 break;
540
541 p += bytes;
542 result += bytes;
543 len -= bytes;
544 }
545
546 close(fd);
547 CopyIn(tc, vaddr, buf, result);
548 delete [] buf;
549 return result;
550}
551
552uint64_t
553writefile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset,
554 Addr filename_addr)
555{
556 DPRINTF(PseudoInst, "PseudoInst::writefile(0x%x, 0x%x, 0x%x, 0x%x)\n",
557 vaddr, len, offset, filename_addr);
558 ostream *os;
559
560 // copy out target filename
561 char fn[100];
562 std::string filename;
563 CopyStringOut(tc, fn, filename_addr, 100);
564 filename = std::string(fn);
565
566 if (offset == 0) {
567 // create a new file (truncate)
568 os = simout.create(filename, true);
569 } else {
570 // do not truncate file if offset is non-zero
571 // (ios::in flag is required as well to keep the existing data
572 // intact, otherwise existing data will be zeroed out.)
573 os = simout.openFile(simout.directory() + filename,
574 ios::in | ios::out | ios::binary);
575 }
576 if (!os)
577 panic("could not open file %s\n", filename);
578
579 // seek to offset
580 os->seekp(offset);
581
582 // copy out data and write to file
583 char *buf = new char[len];
584 CopyOut(tc, buf, vaddr, len);
585 os->write(buf, len);
586 if (os->fail() || os->bad())
587 panic("Error while doing writefile!\n");
588
589 simout.close(os);
590
591 delete [] buf;
592
593 return len;
594}
595
596void
597debugbreak(ThreadContext *tc)
598{
599 DPRINTF(PseudoInst, "PseudoInst::debugbreak()\n");
600 Debug::breakpoint();
601}
602
603void
604switchcpu(ThreadContext *tc)
605{
606 DPRINTF(PseudoInst, "PseudoInst::switchcpu()\n");
607 exitSimLoop("switchcpu");
608}
609
610//
611// This function is executed when annotated work items begin. Depending on
612// what the user specified at the command line, the simulation may exit and/or
613// take a checkpoint when a certain work item begins.
614//
615void
616workbegin(ThreadContext *tc, uint64_t workid, uint64_t threadid)
617{
618 DPRINTF(PseudoInst, "PseudoInst::workbegin(%i, %i)\n", workid, threadid);
619 tc->getCpuPtr()->workItemBegin();
620 System *sys = tc->getSystemPtr();
621 const System::Params *params = sys->params();
622 sys->workItemBegin(threadid, workid);
623
624 DPRINTF(WorkItems, "Work Begin workid: %d, threadid %d\n", workid,
625 threadid);
626
627 //
628 // If specified, determine if this is the specific work item the user
629 // identified
630 //
631 if (params->work_item_id == -1 || params->work_item_id == workid) {
632
633 uint64_t systemWorkBeginCount = sys->incWorkItemsBegin();
634 int cpuId = tc->getCpuPtr()->cpuId();
635
636 if (params->work_cpus_ckpt_count != 0 &&
637 sys->markWorkItem(cpuId) >= params->work_cpus_ckpt_count) {
638 //
639 // If active cpus equals checkpoint count, create checkpoint
640 //
641 exitSimLoop("checkpoint");
642 }
643
644 if (systemWorkBeginCount == params->work_begin_ckpt_count) {
645 //
646 // Note: the string specified as the cause of the exit event must
647 // exactly equal "checkpoint" inorder to create a checkpoint
648 //
649 exitSimLoop("checkpoint");
650 }
651
652 if (systemWorkBeginCount == params->work_begin_exit_count) {
653 //
654 // If a certain number of work items started, exit simulation
655 //
656 exitSimLoop("work started count reach");
657 }
658
659 if (cpuId == params->work_begin_cpu_id_exit) {
660 //
661 // If work started on the cpu id specified, exit simulation
662 //
663 exitSimLoop("work started on specific cpu");
664 }
665 }
666}
667
668//
669// This function is executed when annotated work items end. Depending on
670// what the user specified at the command line, the simulation may exit and/or
671// take a checkpoint when a certain work item ends.
672//
673void
674workend(ThreadContext *tc, uint64_t workid, uint64_t threadid)
675{
676 DPRINTF(PseudoInst, "PseudoInst::workend(%i, %i)\n", workid, threadid);
677 tc->getCpuPtr()->workItemEnd();
678 System *sys = tc->getSystemPtr();
679 const System::Params *params = sys->params();
680 sys->workItemEnd(threadid, workid);
681
682 DPRINTF(WorkItems, "Work End workid: %d, threadid %d\n", workid, threadid);
683
684 //
685 // If specified, determine if this is the specific work item the user
686 // identified
687 //
688 if (params->work_item_id == -1 || params->work_item_id == workid) {
689
690 uint64_t systemWorkEndCount = sys->incWorkItemsEnd();
691 int cpuId = tc->getCpuPtr()->cpuId();
692
693 if (params->work_cpus_ckpt_count != 0 &&
694 sys->markWorkItem(cpuId) >= params->work_cpus_ckpt_count) {
695 //
696 // If active cpus equals checkpoint count, create checkpoint
697 //
698 exitSimLoop("checkpoint");
699 }
700
701 if (params->work_end_ckpt_count != 0 &&
702 systemWorkEndCount == params->work_end_ckpt_count) {
703 //
704 // If total work items completed equals checkpoint count, create
705 // checkpoint
706 //
707 exitSimLoop("checkpoint");
708 }
709
710 if (params->work_end_exit_count != 0 &&
711 systemWorkEndCount == params->work_end_exit_count) {
712 //
713 // If total work items completed equals exit count, exit simulation
714 //
715 exitSimLoop("work items exit count reached");
716 }
717 }
718}
719
720} // namespace PseudoInst