1/*
2 * Copyright (c) 2003-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 */
30
31#include <errno.h>
32#include <fcntl.h>
33#include <unistd.h>
34
35#include <fstream>
36#include <string>
37
38#include "arch/vtophys.hh"
39#include "base/debug.hh"
40#include "config/full_system.hh"
41#include "config/the_isa.hh"
42#include "cpu/base.hh"
43#include "cpu/thread_context.hh"
44#include "cpu/quiesce_event.hh"
45#include "params/BaseCPU.hh"
46#include "sim/pseudo_inst.hh"
47#include "sim/serialize.hh"
48#include "sim/sim_events.hh"
49#include "sim/sim_exit.hh"
50#include "sim/stat_control.hh"
51#include "sim/stats.hh"
52#include "sim/system.hh"
53
54#if FULL_SYSTEM
55#include "arch/kernel_stats.hh"
56#include "sim/vptr.hh"
57#endif
58
59using namespace std;
60
61using namespace Stats;
62using namespace TheISA;
63
64namespace PseudoInst {
65
66#if FULL_SYSTEM
67
68void
69arm(ThreadContext *tc)
70{
71 if (tc->getKernelStats())
72 tc->getKernelStats()->arm();
73}
74
75void
76quiesce(ThreadContext *tc)
77{
78 if (!tc->getCpuPtr()->params()->do_quiesce)
79 return;
80
81 DPRINTF(Quiesce, "%s: quiesce()\n", tc->getCpuPtr()->name());
82
83 tc->suspend();
84 if (tc->getKernelStats())
85 tc->getKernelStats()->quiesce();
86}
87
88void
89quiesceNs(ThreadContext *tc, uint64_t ns)
90{
91 BaseCPU *cpu = tc->getCpuPtr();
92
93 if (!cpu->params()->do_quiesce || ns == 0)
94 return;
95
96 EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
97
| 1/*
2 * Copyright (c) 2003-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Nathan Binkert
29 */
30
31#include <errno.h>
32#include <fcntl.h>
33#include <unistd.h>
34
35#include <fstream>
36#include <string>
37
38#include "arch/vtophys.hh"
39#include "base/debug.hh"
40#include "config/full_system.hh"
41#include "config/the_isa.hh"
42#include "cpu/base.hh"
43#include "cpu/thread_context.hh"
44#include "cpu/quiesce_event.hh"
45#include "params/BaseCPU.hh"
46#include "sim/pseudo_inst.hh"
47#include "sim/serialize.hh"
48#include "sim/sim_events.hh"
49#include "sim/sim_exit.hh"
50#include "sim/stat_control.hh"
51#include "sim/stats.hh"
52#include "sim/system.hh"
53
54#if FULL_SYSTEM
55#include "arch/kernel_stats.hh"
56#include "sim/vptr.hh"
57#endif
58
59using namespace std;
60
61using namespace Stats;
62using namespace TheISA;
63
64namespace PseudoInst {
65
66#if FULL_SYSTEM
67
68void
69arm(ThreadContext *tc)
70{
71 if (tc->getKernelStats())
72 tc->getKernelStats()->arm();
73}
74
75void
76quiesce(ThreadContext *tc)
77{
78 if (!tc->getCpuPtr()->params()->do_quiesce)
79 return;
80
81 DPRINTF(Quiesce, "%s: quiesce()\n", tc->getCpuPtr()->name());
82
83 tc->suspend();
84 if (tc->getKernelStats())
85 tc->getKernelStats()->quiesce();
86}
87
88void
89quiesceNs(ThreadContext *tc, uint64_t ns)
90{
91 BaseCPU *cpu = tc->getCpuPtr();
92
93 if (!cpu->params()->do_quiesce || ns == 0)
94 return;
95
96 EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
97
|
98 Tick resume = curTick + SimClock::Int::ns * ns;
| 98 Tick resume = curTick() + SimClock::Int::ns * ns;
|
99
100 cpu->reschedule(quiesceEvent, resume, true);
101
102 DPRINTF(Quiesce, "%s: quiesceNs(%d) until %d\n",
103 cpu->name(), ns, resume);
104
105 tc->suspend();
106 if (tc->getKernelStats())
107 tc->getKernelStats()->quiesce();
108}
109
110void
111quiesceCycles(ThreadContext *tc, uint64_t cycles)
112{
113 BaseCPU *cpu = tc->getCpuPtr();
114
115 if (!cpu->params()->do_quiesce || cycles == 0)
116 return;
117
118 EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
119
| 99
100 cpu->reschedule(quiesceEvent, resume, true);
101
102 DPRINTF(Quiesce, "%s: quiesceNs(%d) until %d\n",
103 cpu->name(), ns, resume);
104
105 tc->suspend();
106 if (tc->getKernelStats())
107 tc->getKernelStats()->quiesce();
108}
109
110void
111quiesceCycles(ThreadContext *tc, uint64_t cycles)
112{
113 BaseCPU *cpu = tc->getCpuPtr();
114
115 if (!cpu->params()->do_quiesce || cycles == 0)
116 return;
117
118 EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
119
|
120 Tick resume = curTick + cpu->ticks(cycles);
| 120 Tick resume = curTick() + cpu->ticks(cycles);
|
121
122 cpu->reschedule(quiesceEvent, resume, true);
123
124 DPRINTF(Quiesce, "%s: quiesceCycles(%d) until %d\n",
125 cpu->name(), cycles, resume);
126
127 tc->suspend();
128 if (tc->getKernelStats())
129 tc->getKernelStats()->quiesce();
130}
131
132uint64_t
133quiesceTime(ThreadContext *tc)
134{
135 return (tc->readLastActivate() - tc->readLastSuspend()) /
136 SimClock::Int::ns;
137}
138
139#endif
140
141uint64_t
142rpns(ThreadContext *tc)
143{
| 121
122 cpu->reschedule(quiesceEvent, resume, true);
123
124 DPRINTF(Quiesce, "%s: quiesceCycles(%d) until %d\n",
125 cpu->name(), cycles, resume);
126
127 tc->suspend();
128 if (tc->getKernelStats())
129 tc->getKernelStats()->quiesce();
130}
131
132uint64_t
133quiesceTime(ThreadContext *tc)
134{
135 return (tc->readLastActivate() - tc->readLastSuspend()) /
136 SimClock::Int::ns;
137}
138
139#endif
140
141uint64_t
142rpns(ThreadContext *tc)
143{
|
144 return curTick / SimClock::Int::ns;
| 144 return curTick() / SimClock::Int::ns;
|
145}
146
147void
148wakeCPU(ThreadContext *tc, uint64_t cpuid)
149{
150 System *sys = tc->getSystemPtr();
151 ThreadContext *other_tc = sys->threadContexts[cpuid];
152 if (other_tc->status() == ThreadContext::Suspended)
153 other_tc->activate();
154}
155
156void
157m5exit(ThreadContext *tc, Tick delay)
158{
| 145}
146
147void
148wakeCPU(ThreadContext *tc, uint64_t cpuid)
149{
150 System *sys = tc->getSystemPtr();
151 ThreadContext *other_tc = sys->threadContexts[cpuid];
152 if (other_tc->status() == ThreadContext::Suspended)
153 other_tc->activate();
154}
155
156void
157m5exit(ThreadContext *tc, Tick delay)
158{
|
159 Tick when = curTick + delay * SimClock::Int::ns;
| 159 Tick when = curTick() + delay * SimClock::Int::ns;
|
160 exitSimLoop("m5_exit instruction encountered", 0, when);
161}
162
163#if FULL_SYSTEM
164
165void
166loadsymbol(ThreadContext *tc)
167{
168 const string &filename = tc->getCpuPtr()->system->params()->symbolfile;
169 if (filename.empty()) {
170 return;
171 }
172
173 std::string buffer;
174 ifstream file(filename.c_str());
175
176 if (!file)
177 fatal("file error: Can't open symbol table file %s\n", filename);
178
179 while (!file.eof()) {
180 getline(file, buffer);
181
182 if (buffer.empty())
183 continue;
184
185 string::size_type idx = buffer.find(' ');
186 if (idx == string::npos)
187 continue;
188
189 string address = "0x" + buffer.substr(0, idx);
190 eat_white(address);
191 if (address.empty())
192 continue;
193
194 // Skip over letter and space
195 string symbol = buffer.substr(idx + 3);
196 eat_white(symbol);
197 if (symbol.empty())
198 continue;
199
200 Addr addr;
201 if (!to_number(address, addr))
202 continue;
203
204 if (!tc->getSystemPtr()->kernelSymtab->insert(addr, symbol))
205 continue;
206
207
208 DPRINTF(Loader, "Loaded symbol: %s @ %#llx\n", symbol, addr);
209 }
210 file.close();
211}
212
213void
214addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr)
215{
216 char symb[100];
217 CopyStringOut(tc, symb, symbolAddr, 100);
218 std::string symbol(symb);
219
220 DPRINTF(Loader, "Loaded symbol: %s @ %#llx\n", symbol, addr);
221
222 tc->getSystemPtr()->kernelSymtab->insert(addr,symbol);
223 debugSymbolTable->insert(addr,symbol);
224}
225
226#endif
227
228
229void
230resetstats(ThreadContext *tc, Tick delay, Tick period)
231{
232 if (!tc->getCpuPtr()->params()->do_statistics_insts)
233 return;
234
235
| 160 exitSimLoop("m5_exit instruction encountered", 0, when);
161}
162
163#if FULL_SYSTEM
164
165void
166loadsymbol(ThreadContext *tc)
167{
168 const string &filename = tc->getCpuPtr()->system->params()->symbolfile;
169 if (filename.empty()) {
170 return;
171 }
172
173 std::string buffer;
174 ifstream file(filename.c_str());
175
176 if (!file)
177 fatal("file error: Can't open symbol table file %s\n", filename);
178
179 while (!file.eof()) {
180 getline(file, buffer);
181
182 if (buffer.empty())
183 continue;
184
185 string::size_type idx = buffer.find(' ');
186 if (idx == string::npos)
187 continue;
188
189 string address = "0x" + buffer.substr(0, idx);
190 eat_white(address);
191 if (address.empty())
192 continue;
193
194 // Skip over letter and space
195 string symbol = buffer.substr(idx + 3);
196 eat_white(symbol);
197 if (symbol.empty())
198 continue;
199
200 Addr addr;
201 if (!to_number(address, addr))
202 continue;
203
204 if (!tc->getSystemPtr()->kernelSymtab->insert(addr, symbol))
205 continue;
206
207
208 DPRINTF(Loader, "Loaded symbol: %s @ %#llx\n", symbol, addr);
209 }
210 file.close();
211}
212
213void
214addsymbol(ThreadContext *tc, Addr addr, Addr symbolAddr)
215{
216 char symb[100];
217 CopyStringOut(tc, symb, symbolAddr, 100);
218 std::string symbol(symb);
219
220 DPRINTF(Loader, "Loaded symbol: %s @ %#llx\n", symbol, addr);
221
222 tc->getSystemPtr()->kernelSymtab->insert(addr,symbol);
223 debugSymbolTable->insert(addr,symbol);
224}
225
226#endif
227
228
229void
230resetstats(ThreadContext *tc, Tick delay, Tick period)
231{
232 if (!tc->getCpuPtr()->params()->do_statistics_insts)
233 return;
234
235
|
236 Tick when = curTick + delay * SimClock::Int::ns;
| 236 Tick when = curTick() + delay * SimClock::Int::ns;
|
237 Tick repeat = period * SimClock::Int::ns;
238
239 Stats::schedStatEvent(false, true, when, repeat);
240}
241
242void
243dumpstats(ThreadContext *tc, Tick delay, Tick period)
244{
245 if (!tc->getCpuPtr()->params()->do_statistics_insts)
246 return;
247
248
| 237 Tick repeat = period * SimClock::Int::ns;
238
239 Stats::schedStatEvent(false, true, when, repeat);
240}
241
242void
243dumpstats(ThreadContext *tc, Tick delay, Tick period)
244{
245 if (!tc->getCpuPtr()->params()->do_statistics_insts)
246 return;
247
248
|
249 Tick when = curTick + delay * SimClock::Int::ns;
| 249 Tick when = curTick() + delay * SimClock::Int::ns;
|
250 Tick repeat = period * SimClock::Int::ns;
251
252 Stats::schedStatEvent(true, false, when, repeat);
253}
254
255void
256dumpresetstats(ThreadContext *tc, Tick delay, Tick period)
257{
258 if (!tc->getCpuPtr()->params()->do_statistics_insts)
259 return;
260
261
| 250 Tick repeat = period * SimClock::Int::ns;
251
252 Stats::schedStatEvent(true, false, when, repeat);
253}
254
255void
256dumpresetstats(ThreadContext *tc, Tick delay, Tick period)
257{
258 if (!tc->getCpuPtr()->params()->do_statistics_insts)
259 return;
260
261
|
262 Tick when = curTick + delay * SimClock::Int::ns;
| 262 Tick when = curTick() + delay * SimClock::Int::ns;
|
263 Tick repeat = period * SimClock::Int::ns;
264
265 Stats::schedStatEvent(true, true, when, repeat);
266}
267
268void
269m5checkpoint(ThreadContext *tc, Tick delay, Tick period)
270{
271 if (!tc->getCpuPtr()->params()->do_checkpoint_insts)
272 return;
273
| 263 Tick repeat = period * SimClock::Int::ns;
264
265 Stats::schedStatEvent(true, true, when, repeat);
266}
267
268void
269m5checkpoint(ThreadContext *tc, Tick delay, Tick period)
270{
271 if (!tc->getCpuPtr()->params()->do_checkpoint_insts)
272 return;
273
|
274 Tick when = curTick + delay * SimClock::Int::ns;
| 274 Tick when = curTick() + delay * SimClock::Int::ns;
|
275 Tick repeat = period * SimClock::Int::ns;
276
277 exitSimLoop("checkpoint", 0, when, repeat);
278}
279
280#if FULL_SYSTEM
281
282uint64_t
283readfile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset)
284{
285 const string &file = tc->getSystemPtr()->params()->readfile;
286 if (file.empty()) {
287 return ULL(0);
288 }
289
290 uint64_t result = 0;
291
292 int fd = ::open(file.c_str(), O_RDONLY, 0);
293 if (fd < 0)
294 panic("could not open file %s\n", file);
295
296 if (::lseek(fd, offset, SEEK_SET) < 0)
297 panic("could not seek: %s", strerror(errno));
298
299 char *buf = new char[len];
300 char *p = buf;
301 while (len > 0) {
302 int bytes = ::read(fd, p, len);
303 if (bytes <= 0)
304 break;
305
306 p += bytes;
307 result += bytes;
308 len -= bytes;
309 }
310
311 close(fd);
312 CopyIn(tc, vaddr, buf, result);
313 delete [] buf;
314 return result;
315}
316
317#endif
318
319void
320debugbreak(ThreadContext *tc)
321{
322 debug_break();
323}
324
325void
326switchcpu(ThreadContext *tc)
327{
328 exitSimLoop("switchcpu");
329}
330
331} // namespace PseudoInst
| 275 Tick repeat = period * SimClock::Int::ns;
276
277 exitSimLoop("checkpoint", 0, when, repeat);
278}
279
280#if FULL_SYSTEM
281
282uint64_t
283readfile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset)
284{
285 const string &file = tc->getSystemPtr()->params()->readfile;
286 if (file.empty()) {
287 return ULL(0);
288 }
289
290 uint64_t result = 0;
291
292 int fd = ::open(file.c_str(), O_RDONLY, 0);
293 if (fd < 0)
294 panic("could not open file %s\n", file);
295
296 if (::lseek(fd, offset, SEEK_SET) < 0)
297 panic("could not seek: %s", strerror(errno));
298
299 char *buf = new char[len];
300 char *p = buf;
301 while (len > 0) {
302 int bytes = ::read(fd, p, len);
303 if (bytes <= 0)
304 break;
305
306 p += bytes;
307 result += bytes;
308 len -= bytes;
309 }
310
311 close(fd);
312 CopyIn(tc, vaddr, buf, result);
313 delete [] buf;
314 return result;
315}
316
317#endif
318
319void
320debugbreak(ThreadContext *tc)
321{
322 debug_break();
323}
324
325void
326switchcpu(ThreadContext *tc)
327{
328 exitSimLoop("switchcpu");
329}
330
331} // namespace PseudoInst
|