1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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47#include <cerrno>
48#include <fstream>
49#include <string>
50#include <vector>
51
52#include "arch/kernel_stats.hh"
53#include "arch/utility.hh"
54#include "arch/vtophys.hh"
55#include "base/debug.hh"
56#include "base/output.hh"
57#include "config/the_isa.hh"
58#include "cpu/base.hh"
59#include "cpu/quiesce_event.hh"
60#include "cpu/thread_context.hh"
61#include "debug/Loader.hh"
62#include "debug/PseudoInst.hh"
63#include "debug/Quiesce.hh"
64#include "debug/WorkItems.hh"
65#include "params/BaseCPU.hh"
66#include "sim/full_system.hh"
67#include "sim/pseudo_inst.hh"
68#include "sim/serialize.hh"
69#include "sim/sim_events.hh"
70#include "sim/sim_exit.hh"
71#include "sim/stat_control.hh"
72#include "sim/stats.hh"
73#include "sim/system.hh"
74#include "sim/vptr.hh"

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193 case 0x55: // annotate_func
194 case 0x56: // reserved2_func
195 case 0x57: // reserved3_func
196 case 0x58: // reserved4_func
197 case 0x59: // reserved5_func
198 warn("Unimplemented m5 op (0x%x)\n", func);
199 break;
200
201 default:
202 warn("Unhandled m5 op: 0x%x\n", func);
203 break;
204 }
205
206 return 0;
207}
208

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