1/*
2 * Copyright (c) 2003-2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 26 unchanged lines hidden (view full) ---

35#include <string>
36
37#include "arch/vtophys.hh"
38#include "base/annotate.hh"
39#include "cpu/base.hh"
40#include "cpu/thread_context.hh"
41#include "cpu/quiesce_event.hh"
42#include "arch/kernel_stats.hh"
43#include "sim/param.hh"
44#include "sim/pseudo_inst.hh"
45#include "sim/serialize.hh"
46#include "sim/sim_exit.hh"
47#include "sim/stat_control.hh"
48#include "sim/stats.hh"
49#include "sim/system.hh"
50#include "sim/debug.hh"
51#include "sim/vptr.hh"
52
53using namespace std;
54
55using namespace Stats;
56using namespace TheISA;
57
58namespace AlphaPseudo
59{
60 bool doStatisticsInsts;
61 bool doCheckpointInsts;
62 bool doQuiesce;
63
64 void
65 arm(ThreadContext *tc)
66 {
67 if (tc->getKernelStats())
68 tc->getKernelStats()->arm();
69 }
70
71 void
72 quiesce(ThreadContext *tc)
73 {
74 if (!doQuiesce)
75 return;
76
77 DPRINTF(Quiesce, "%s: quiesce()\n", tc->getCpuPtr()->name());
78
79 tc->suspend();
80 if (tc->getKernelStats())
81 tc->getKernelStats()->quiesce();
82 }
83
84 void
85 quiesceNs(ThreadContext *tc, uint64_t ns)
86 {
87 if (!doQuiesce || ns == 0)
88 return;
89
90 EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
91
92 Tick resume = curTick + Clock::Int::ns * ns;
93
94 if (quiesceEvent->scheduled())
95 quiesceEvent->reschedule(resume);

--- 6 unchanged lines hidden (view full) ---

102 tc->suspend();
103 if (tc->getKernelStats())
104 tc->getKernelStats()->quiesce();
105 }
106
107 void
108 quiesceCycles(ThreadContext *tc, uint64_t cycles)
109 {
110 if (!doQuiesce || cycles == 0)
111 return;
112
113 EndQuiesceEvent *quiesceEvent = tc->getQuiesceEvent();
114
115 Tick resume = curTick + tc->getCpuPtr()->cycles(cycles);
116
117 if (quiesceEvent->scheduled())
118 quiesceEvent->reschedule(resume);

--- 73 unchanged lines hidden (view full) ---

192 DPRINTF(Loader, "Loaded symbol: %s @ %#llx\n", symbol, addr);
193 }
194 file.close();
195 }
196
197 void
198 resetstats(ThreadContext *tc, Tick delay, Tick period)
199 {
200 if (!doStatisticsInsts)
201 return;
202
203
204 Tick when = curTick + delay * Clock::Int::ns;
205 Tick repeat = period * Clock::Int::ns;
206
207 using namespace Stats;
208 SetupEvent(Reset, when, repeat);
209 }
210
211 void
212 dumpstats(ThreadContext *tc, Tick delay, Tick period)
213 {
214 if (!doStatisticsInsts)
215 return;
216
217
218 Tick when = curTick + delay * Clock::Int::ns;
219 Tick repeat = period * Clock::Int::ns;
220
221 using namespace Stats;
222 SetupEvent(Dump, when, repeat);

--- 24 unchanged lines hidden (view full) ---

247 Annotate::annotations.add(tc->getSystemPtr(), 0, cur >> 32, cur &
248 0xFFFFFFFF, wait >> 32, wait & 0xFFFFFFFF);
249 }
250
251
252 void
253 dumpresetstats(ThreadContext *tc, Tick delay, Tick period)
254 {
255 if (!doStatisticsInsts)
256 return;
257
258
259 Tick when = curTick + delay * Clock::Int::ns;
260 Tick repeat = period * Clock::Int::ns;
261
262 using namespace Stats;
263 SetupEvent(Dump|Reset, when, repeat);
264 }
265
266 void
267 m5checkpoint(ThreadContext *tc, Tick delay, Tick period)
268 {
269 if (!doCheckpointInsts)
270 return;
271
272 Tick when = curTick + delay * Clock::Int::ns;
273 Tick repeat = period * Clock::Int::ns;
274
275 schedExitSimLoop("checkpoint", when, repeat);
276 }
277
278 uint64_t
279 readfile(ThreadContext *tc, Addr vaddr, uint64_t len, uint64_t offset)
280 {
281 const string &file = tc->getCpuPtr()->system->params()->readfile;
282 if (file.empty()) {
283 return ULL(0);
284 }
285
286 uint64_t result = 0;
287
288 int fd = ::open(file.c_str(), O_RDONLY, 0);
289 if (fd < 0)

--- 15 unchanged lines hidden (view full) ---

305 }
306
307 close(fd);
308 CopyIn(tc, vaddr, buf, result);
309 delete [] buf;
310 return result;
311 }
312
313 class Context : public ParamContext
314 {
315 public:
316 Context(const string &section) : ParamContext(section) {}
317 void checkParams();
318 };
319
320 Context context("pseudo_inst");
321
322 Param<bool> __quiesce(&context, "quiesce",
323 "enable quiesce instructions",
324 true);
325 Param<bool> __statistics(&context, "statistics",
326 "enable statistics pseudo instructions",
327 true);
328 Param<bool> __checkpoint(&context, "checkpoint",
329 "enable checkpoint pseudo instructions",
330 true);
331
332 void
333 Context::checkParams()
334 {
335 doQuiesce = __quiesce;
336 doStatisticsInsts = __statistics;
337 doCheckpointInsts = __checkpoint;
338 }
339
340 void debugbreak(ThreadContext *tc)
341 {
342 debug_break();
343 }
344
345 void switchcpu(ThreadContext *tc)
346 {
347 exitSimLoop("switchcpu");
348 }
349}