SConscript (9983:2cce74fe359e) SConscript (10249:6bbb7ae309ac)
1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright

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31Import('*')
32
33SimObject('BaseTLB.py')
34SimObject('ClockedObject.py')
35SimObject('Root.py')
36SimObject('ClockDomain.py')
37SimObject('VoltageDomain.py')
38SimObject('System.py')
1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright

--- 22 unchanged lines hidden (view full) ---

31Import('*')
32
33SimObject('BaseTLB.py')
34SimObject('ClockedObject.py')
35SimObject('Root.py')
36SimObject('ClockDomain.py')
37SimObject('VoltageDomain.py')
38SimObject('System.py')
39SimObject('DVFSHandler.py')
39
40Source('arguments.cc')
41Source('async.cc')
42Source('core.cc')
43Source('debug.cc')
44Source('eventq.cc')
45Source('global_event.cc')
46Source('init.cc')
47Source('main.cc', main=True, skip_lib=True)
48Source('root.cc')
49Source('serialize.cc')
50Source('drain.cc')
51Source('sim_events.cc')
52Source('sim_object.cc')
53Source('simulate.cc')
54Source('stat_control.cc')
55Source('clock_domain.cc')
56Source('voltage_domain.cc')
57Source('system.cc')
40
41Source('arguments.cc')
42Source('async.cc')
43Source('core.cc')
44Source('debug.cc')
45Source('eventq.cc')
46Source('global_event.cc')
47Source('init.cc')
48Source('main.cc', main=True, skip_lib=True)
49Source('root.cc')
50Source('serialize.cc')
51Source('drain.cc')
52Source('sim_events.cc')
53Source('sim_object.cc')
54Source('simulate.cc')
55Source('stat_control.cc')
56Source('clock_domain.cc')
57Source('voltage_domain.cc')
58Source('system.cc')
59Source('dvfs_handler.cc')
58
59if env['TARGET_ISA'] != 'null':
60 SimObject('InstTracer.py')
61 SimObject('Process.py')
62 Source('faults.cc')
63 Source('process.cc')
64 Source('pseudo_inst.cc')
65 Source('syscall_emul.cc')

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81DebugFlag('TimeSync')
82DebugFlag('TLB')
83DebugFlag('Thread')
84DebugFlag('Timer')
85DebugFlag('VtoPhys')
86DebugFlag('WorkItems')
87DebugFlag('ClockDomain')
88DebugFlag('VoltageDomain')
60
61if env['TARGET_ISA'] != 'null':
62 SimObject('InstTracer.py')
63 SimObject('Process.py')
64 Source('faults.cc')
65 Source('process.cc')
66 Source('pseudo_inst.cc')
67 Source('syscall_emul.cc')

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83DebugFlag('TimeSync')
84DebugFlag('TLB')
85DebugFlag('Thread')
86DebugFlag('Timer')
87DebugFlag('VtoPhys')
88DebugFlag('WorkItems')
89DebugFlag('ClockDomain')
90DebugFlag('VoltageDomain')
91DebugFlag('DVFS')