SConscript (8770:81354d3836d4) | SConscript (8774:232b5574d9c3) |
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1# -*- mode:python -*- 2 3# Copyright (c) 2006 The Regents of The University of Michigan 4# All rights reserved. 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are 8# met: redistributions of source code must retain the above copyright --- 20 unchanged lines hidden (view full) --- 29# Authors: Nathan Binkert 30 31Import('*') 32 33SimObject('BaseTLB.py') 34SimObject('Root.py') 35SimObject('InstTracer.py') 36 | 1# -*- mode:python -*- 2 3# Copyright (c) 2006 The Regents of The University of Michigan 4# All rights reserved. 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are 8# met: redistributions of source code must retain the above copyright --- 20 unchanged lines hidden (view full) --- 29# Authors: Nathan Binkert 30 31Import('*') 32 33SimObject('BaseTLB.py') 34SimObject('Root.py') 35SimObject('InstTracer.py') 36 |
37Source('arguments.cc') |
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37Source('async.cc') 38Source('core.cc') 39Source('debug.cc') 40Source('eventq.cc') 41Source('init.cc') 42Source('main.cc', main=True, skip_lib=True) 43Source('root.cc') 44Source('serialize.cc') --- 6 unchanged lines hidden (view full) --- 51if env['TARGET_ISA'] != 'no': 52 SimObject('Process.py') 53 SimObject('System.py') 54 Source('faults.cc') 55 Source('process.cc') 56 Source('pseudo_inst.cc') 57 Source('system.cc') 58 | 38Source('async.cc') 39Source('core.cc') 40Source('debug.cc') 41Source('eventq.cc') 42Source('init.cc') 43Source('main.cc', main=True, skip_lib=True) 44Source('root.cc') 45Source('serialize.cc') --- 6 unchanged lines hidden (view full) --- 52if env['TARGET_ISA'] != 'no': 53 SimObject('Process.py') 54 SimObject('System.py') 55 Source('faults.cc') 56 Source('process.cc') 57 Source('pseudo_inst.cc') 58 Source('system.cc') 59 |
59if env['FULL_SYSTEM']: 60 Source('arguments.cc') 61elif env['TARGET_ISA'] != 'no': | 60if not env['FULL_SYSTEM'] and env['TARGET_ISA'] != 'no': |
62 Source('tlb.cc') 63 64DebugFlag('Checkpoint') 65DebugFlag('Config') 66DebugFlag('Event') 67DebugFlag('Fault') 68DebugFlag('Flow') 69DebugFlag('IPI') 70DebugFlag('IPR') 71DebugFlag('Interrupt') 72DebugFlag('Loader') 73DebugFlag('Stack') 74DebugFlag('SyscallVerbose') 75DebugFlag('TimeSync') 76DebugFlag('TLB') 77DebugFlag('Thread') 78DebugFlag('Timer') 79DebugFlag('VtoPhys') 80DebugFlag('WorkItems') | 61 Source('tlb.cc') 62 63DebugFlag('Checkpoint') 64DebugFlag('Config') 65DebugFlag('Event') 66DebugFlag('Fault') 67DebugFlag('Flow') 68DebugFlag('IPI') 69DebugFlag('IPR') 70DebugFlag('Interrupt') 71DebugFlag('Loader') 72DebugFlag('Stack') 73DebugFlag('SyscallVerbose') 74DebugFlag('TimeSync') 75DebugFlag('TLB') 76DebugFlag('Thread') 77DebugFlag('Timer') 78DebugFlag('VtoPhys') 79DebugFlag('WorkItems') |