SConscript (7733:08d6a773d1b6) SConscript (7768:cdb18c1b51ea)
1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright

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27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28#
29# Authors: Nathan Binkert
30
31Import('*')
32
33SimObject('BaseTLB.py')
34SimObject('Root.py')
1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright

--- 18 unchanged lines hidden (view full) ---

27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28#
29# Authors: Nathan Binkert
30
31Import('*')
32
33SimObject('BaseTLB.py')
34SimObject('Root.py')
35SimObject('System.py')
36SimObject('InstTracer.py')
37
38Source('async.cc')
39Source('core.cc')
40Source('debug.cc')
41Source('eventq.cc')
35SimObject('InstTracer.py')
36
37Source('async.cc')
38Source('core.cc')
39Source('debug.cc')
40Source('eventq.cc')
42Source('faults.cc')
43Source('init.cc')
44Source('main.cc', bin_only=True)
41Source('init.cc')
42Source('main.cc', bin_only=True)
45Source('pseudo_inst.cc')
46Source('root.cc')
47Source('serialize.cc')
48Source('sim_events.cc')
49Source('sim_object.cc')
50Source('simulate.cc')
51Source('stat_control.cc')
43Source('root.cc')
44Source('serialize.cc')
45Source('sim_events.cc')
46Source('sim_object.cc')
47Source('simulate.cc')
48Source('stat_control.cc')
52Source('system.cc')
53
49
50if env['TARGET_ISA'] != 'no':
51 SimObject('System.py')
52 Source('faults.cc')
53 Source('pseudo_inst.cc')
54 Source('system.cc')
55
54if env['FULL_SYSTEM']:
55 Source('arguments.cc')
56if env['FULL_SYSTEM']:
57 Source('arguments.cc')
56else:
58elif env['TARGET_ISA'] != 'no':
57 Source('tlb.cc')
58 SimObject('Process.py')
59
60 Source('process.cc')
61 Source('syscall_emul.cc')
62
63TraceFlag('Checkpoint')
64TraceFlag('Config')

--- 13 unchanged lines hidden --- 		59 Source('tlb.cc')
60 SimObject('Process.py')
61
62 Source('process.cc')
63 Source('syscall_emul.cc')
64
65TraceFlag('Checkpoint')
66TraceFlag('Config')

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