SConscript (11430:bd1c6789c33f) | SConscript (11524:3101ce98c55c) |
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1# -*- mode:python -*- 2 3# Copyright (c) 2006 The Regents of The University of Michigan 4# All rights reserved. 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are 8# met: redistributions of source code must retain the above copyright --- 55 unchanged lines hidden (view full) --- 64Source('simulate.cc') 65Source('stat_control.cc') 66Source('stat_register.cc', skip_no_python=True) 67Source('clock_domain.cc') 68Source('voltage_domain.cc') 69Source('linear_solver.cc') 70Source('system.cc') 71Source('dvfs_handler.cc') | 1# -*- mode:python -*- 2 3# Copyright (c) 2006 The Regents of The University of Michigan 4# All rights reserved. 5# 6# Redistribution and use in source and binary forms, with or without 7# modification, are permitted provided that the following conditions are 8# met: redistributions of source code must retain the above copyright --- 55 unchanged lines hidden (view full) --- 64Source('simulate.cc') 65Source('stat_control.cc') 66Source('stat_register.cc', skip_no_python=True) 67Source('clock_domain.cc') 68Source('voltage_domain.cc') 69Source('linear_solver.cc') 70Source('system.cc') 71Source('dvfs_handler.cc') |
72Source('clocked_object.cc') |
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72 73if env['TARGET_ISA'] != 'null': 74 SimObject('InstTracer.py') 75 SimObject('Process.py') 76 Source('faults.cc') 77 Source('process.cc') 78 Source('fd_entry.cc') 79 Source('pseudo_inst.cc') --- 27 unchanged lines hidden --- | 73 74if env['TARGET_ISA'] != 'null': 75 SimObject('InstTracer.py') 76 SimObject('Process.py') 77 Source('faults.cc') 78 Source('process.cc') 79 Source('fd_entry.cc') 80 Source('pseudo_inst.cc') --- 27 unchanged lines hidden --- |