SConscript (10458:64809024b924) SConscript (10687:276da6265ab8)
1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright

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25# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28#
29# Authors: Nathan Binkert
30
31Import('*')
32
1# -*- mode:python -*-
2
3# Copyright (c) 2006 The Regents of The University of Michigan
4# All rights reserved.
5#
6# Redistribution and use in source and binary forms, with or without
7# modification, are permitted provided that the following conditions are
8# met: redistributions of source code must retain the above copyright

--- 16 unchanged lines hidden (view full) ---

25# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
26# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
27# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28#
29# Authors: Nathan Binkert
30
31Import('*')
32
33SimObject('BaseTLB.py')
34SimObject('ClockedObject.py')
35SimObject('TickedObject.py')
36SimObject('Root.py')
37SimObject('ClockDomain.py')
38SimObject('VoltageDomain.py')
39SimObject('System.py')
40SimObject('DVFSHandler.py')
41SimObject('SubSystem.py')

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70
71if env['TARGET_ISA'] != 'null':
72 SimObject('InstTracer.py')
73 SimObject('Process.py')
74 Source('faults.cc')
75 Source('process.cc')
76 Source('pseudo_inst.cc')
77 Source('syscall_emul.cc')
33SimObject('ClockedObject.py')
34SimObject('TickedObject.py')
35SimObject('Root.py')
36SimObject('ClockDomain.py')
37SimObject('VoltageDomain.py')
38SimObject('System.py')
39SimObject('DVFSHandler.py')
40SimObject('SubSystem.py')

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69
70if env['TARGET_ISA'] != 'null':
71 SimObject('InstTracer.py')
72 SimObject('Process.py')
73 Source('faults.cc')
74 Source('process.cc')
75 Source('pseudo_inst.cc')
76 Source('syscall_emul.cc')
78 Source('tlb.cc')
79
80DebugFlag('Checkpoint')
81DebugFlag('Config')
82DebugFlag('CxxConfig')
83DebugFlag('Drain')
84DebugFlag('Event')
85DebugFlag('Fault')
86DebugFlag('Flow')
87DebugFlag('IPI')
88DebugFlag('IPR')
89DebugFlag('Interrupt')
90DebugFlag('Loader')
91DebugFlag('PseudoInst')
92DebugFlag('Stack')
93DebugFlag('SyscallVerbose')
94DebugFlag('TimeSync')
77
78DebugFlag('Checkpoint')
79DebugFlag('Config')
80DebugFlag('CxxConfig')
81DebugFlag('Drain')
82DebugFlag('Event')
83DebugFlag('Fault')
84DebugFlag('Flow')
85DebugFlag('IPI')
86DebugFlag('IPR')
87DebugFlag('Interrupt')
88DebugFlag('Loader')
89DebugFlag('PseudoInst')
90DebugFlag('Stack')
91DebugFlag('SyscallVerbose')
92DebugFlag('TimeSync')
95DebugFlag('TLB')
96DebugFlag('Thread')
97DebugFlag('Timer')
98DebugFlag('VtoPhys')
99DebugFlag('WorkItems')
100DebugFlag('ClockDomain')
101DebugFlag('VoltageDomain')
102DebugFlag('DVFS')
93DebugFlag('Thread')
94DebugFlag('Timer')
95DebugFlag('VtoPhys')
96DebugFlag('WorkItems')
97DebugFlag('ClockDomain')
98DebugFlag('VoltageDomain')
99DebugFlag('DVFS')