RubyPort.hh (9294:8fb03b13de02) RubyPort.hh (9342:6fec8f26e56d)
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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137 virtual void descheduleDeadlockEvent() = 0;
138
139 //
140 // Called by the controller to give the sequencer a pointer.
141 // A pointer to the controller is needed for atomic support.
142 //
143 void setController(AbstractController* _cntrl) { m_controller = _cntrl; }
144 int getId() { return m_version; }
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 128 unchanged lines hidden (view full) ---

137 virtual void descheduleDeadlockEvent() = 0;
138
139 //
140 // Called by the controller to give the sequencer a pointer.
141 // A pointer to the controller is needed for atomic support.
142 //
143 void setController(AbstractController* _cntrl) { m_controller = _cntrl; }
144 int getId() { return m_version; }
145 unsigned int drain(Event *de);
145 unsigned int drain(DrainManager *dm);
146
147 protected:
148 const std::string m_name;
149 void ruby_hit_callback(PacketPtr pkt);
150 void testDrainComplete();
151 void ruby_eviction_callback(const Address& address);
152
153 int m_version;

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161 {
162 if (!port->onRetryList()) {
163 port->onRetryList(true);
164 retryList.push_back(port);
165 waitingOnSequencer = true;
166 }
167 }
168
146
147 protected:
148 const std::string m_name;
149 void ruby_hit_callback(PacketPtr pkt);
150 void testDrainComplete();
151 void ruby_eviction_callback(const Address& address);
152
153 int m_version;

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161 {
162 if (!port->onRetryList()) {
163 port->onRetryList(true);
164 retryList.push_back(port);
165 waitingOnSequencer = true;
166 }
167 }
168
169 unsigned int getChildDrainCount(Event *de);
169 unsigned int getChildDrainCount(DrainManager *dm);
170
171 uint16_t m_port_id;
172 uint64_t m_request_cnt;
173
174 /** Vector of M5 Ports attached to this Ruby port. */
175 typedef std::vector<M5Port*>::iterator CpuPortIter;
176 std::vector<M5Port*> slave_ports;
177 std::vector<PioPort*> master_ports;
178
170
171 uint16_t m_port_id;
172 uint64_t m_request_cnt;
173
174 /** Vector of M5 Ports attached to this Ruby port. */
175 typedef std::vector<M5Port*>::iterator CpuPortIter;
176 std::vector<M5Port*> slave_ports;
177 std::vector<PioPort*> master_ports;
178
179 Event *drainEvent;
179 DrainManager *drainManager;
180
181 RubySystem* ruby_system;
182 System* system;
183
184 //
185 // Based on similar code in the M5 bus. Stores pointers to those ports
186 // that should be called when the Sequencer becomes available after a stall.
187 //
188 std::list<M5Port*> retryList;
189
190 bool waitingOnSequencer;
191 bool access_phys_mem;
192};
193
194#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__
180
181 RubySystem* ruby_system;
182 System* system;
183
184 //
185 // Based on similar code in the M5 bus. Stores pointers to those ports
186 // that should be called when the Sequencer becomes available after a stall.
187 //
188 std::list<M5Port*> retryList;
189
190 bool waitingOnSequencer;
191 bool access_phys_mem;
192};
193
194#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__