RubyPort.hh (8922:17f037ad8918) | RubyPort.hh (8923:820111f58fbb) |
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1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 161 unchanged lines hidden (view full) --- 170 } 171 } 172 173 unsigned int getDrainCount(Event *de); 174 175 uint16_t m_port_id; 176 uint64_t m_request_cnt; 177 | 1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 161 unchanged lines hidden (view full) --- 170 } 171 } 172 173 unsigned int getDrainCount(Event *de); 174 175 uint16_t m_port_id; 176 uint64_t m_request_cnt; 177 |
178 PioPort physMemPort; 179 | |
180 /** Vector of M5 Ports attached to this Ruby port. */ 181 typedef std::vector<M5Port*>::iterator CpuPortIter; 182 std::vector<M5Port*> slave_ports; 183 std::vector<PioPort*> master_ports; 184 185 Event *drainEvent; 186 | 178 /** Vector of M5 Ports attached to this Ruby port. */ 179 typedef std::vector<M5Port*>::iterator CpuPortIter; 180 std::vector<M5Port*> slave_ports; 181 std::vector<PioPort*> master_ports; 182 183 Event *drainEvent; 184 |
187 PhysicalMemory* physmem; | |
188 RubySystem* ruby_system; | 185 RubySystem* ruby_system; |
186 System* system; |
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189 190 // 191 // Based on similar code in the M5 bus. Stores pointers to those ports 192 // that should be called when the Sequencer becomes available after a stall. 193 // 194 std::list<M5Port*> retryList; 195 196 bool waitingOnSequencer; 197 bool access_phys_mem; 198}; 199 200#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__ | 187 188 // 189 // Based on similar code in the M5 bus. Stores pointers to those ports 190 // that should be called when the Sequencer becomes available after a stall. 191 // 192 std::list<M5Port*> retryList; 193 194 bool waitingOnSequencer; 195 bool access_phys_mem; 196}; 197 198#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__ |