RubyPort.hh (6922:1620cffaa3b6) | RubyPort.hh (7039:bc0b6ea676b5) |
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1 | |
2/* 3 * Copyright (c) 2009 Advanced Micro Devices, Inc. 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions are 8 * met: redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer; --- 12 unchanged lines hidden (view full) --- 22 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 23 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 27 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 */ 29 | 1/* 2 * Copyright (c) 2009 Advanced Micro Devices, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 12 unchanged lines hidden (view full) --- 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 |
30#ifndef RUBYPORT_H 31#define RUBYPORT_H | 29#ifndef __MEM_RUBY_SYSTEM_RUBYPORT_HH__ 30#define __MEM_RUBY_SYSTEM_RUBYPORT_HH__ |
32 | 31 |
33#include "mem/ruby/libruby.hh" | 32#include <cassert> |
34#include <string> | 33#include <string> |
35#include <assert.h> | |
36 37#include "mem/mem_object.hh" | 34 35#include "mem/mem_object.hh" |
38#include "mem/tport.hh" | |
39#include "mem/physical.hh" 40#include "mem/protocol/RequestStatus.hh" | 36#include "mem/physical.hh" 37#include "mem/protocol/RequestStatus.hh" |
41 | 38#include "mem/ruby/libruby.hh" 39#include "mem/tport.hh" |
42#include "params/RubyPort.hh" 43 44using namespace std; 45 46class MessageBuffer; 47class AbstractController; 48 | 40#include "params/RubyPort.hh" 41 42using namespace std; 43 44class MessageBuffer; 45class AbstractController; 46 |
49class RubyPort : public MemObject { 50public: 51 | 47class RubyPort : public MemObject 48{ 49 public: |
52 class M5Port : public SimpleTimingPort 53 { | 50 class M5Port : public SimpleTimingPort 51 { |
54 | 52 private: |
55 RubyPort *ruby_port; 56 57 public: | 53 RubyPort *ruby_port; 54 55 public: |
58 M5Port(const std::string &_name, 59 RubyPort *_port); | 56 M5Port(const std::string &_name, RubyPort *_port); |
60 bool sendTiming(PacketPtr pkt); 61 void hitCallback(PacketPtr pkt); 62 63 protected: 64 virtual bool recvTiming(PacketPtr pkt); 65 virtual Tick recvAtomic(PacketPtr pkt); 66 67 private: 68 bool isPhysMemAddress(Addr addr); 69 }; 70 71 friend class M5Port; 72 73 class PioPort : public SimpleTimingPort 74 { | 57 bool sendTiming(PacketPtr pkt); 58 void hitCallback(PacketPtr pkt); 59 60 protected: 61 virtual bool recvTiming(PacketPtr pkt); 62 virtual Tick recvAtomic(PacketPtr pkt); 63 64 private: 65 bool isPhysMemAddress(Addr addr); 66 }; 67 68 friend class M5Port; 69 70 class PioPort : public SimpleTimingPort 71 { |
75 | 72 private: |
76 RubyPort *ruby_port; 77 78 public: | 73 RubyPort *ruby_port; 74 75 public: |
79 PioPort(const std::string &_name, 80 RubyPort *_port); | 76 PioPort(const std::string &_name, RubyPort *_port); |
81 bool sendTiming(PacketPtr pkt); 82 83 protected: 84 virtual bool recvTiming(PacketPtr pkt); 85 virtual Tick recvAtomic(PacketPtr pkt); 86 }; 87 88 friend class PioPort; 89 90 struct SenderState : public Packet::SenderState 91 { 92 M5Port* port; 93 Packet::SenderState *saved; 94 | 77 bool sendTiming(PacketPtr pkt); 78 79 protected: 80 virtual bool recvTiming(PacketPtr pkt); 81 virtual Tick recvAtomic(PacketPtr pkt); 82 }; 83 84 friend class PioPort; 85 86 struct SenderState : public Packet::SenderState 87 { 88 M5Port* port; 89 Packet::SenderState *saved; 90 |
95 SenderState(M5Port* _port, 96 Packet::SenderState *sender_state = NULL) | 91 SenderState(M5Port* _port, Packet::SenderState *sender_state = NULL) |
97 : port(_port), saved(sender_state) 98 {} 99 }; 100 101 typedef RubyPortParams Params; 102 RubyPort(const Params *p); 103 virtual ~RubyPort() {} 104 --- 4 unchanged lines hidden (view full) --- 109 virtual RequestStatus makeRequest(const RubyRequest & request) = 0; 110 111 // 112 // Called by the controller to give the sequencer a pointer. 113 // A pointer to the controller is needed for atomic support. 114 // 115 void setController(AbstractController* _cntrl) { m_controller = _cntrl; } 116 | 92 : port(_port), saved(sender_state) 93 {} 94 }; 95 96 typedef RubyPortParams Params; 97 RubyPort(const Params *p); 98 virtual ~RubyPort() {} 99 --- 4 unchanged lines hidden (view full) --- 104 virtual RequestStatus makeRequest(const RubyRequest & request) = 0; 105 106 // 107 // Called by the controller to give the sequencer a pointer. 108 // A pointer to the controller is needed for atomic support. 109 // 110 void setController(AbstractController* _cntrl) { m_controller = _cntrl; } 111 |
117protected: 118 const string m_name; 119 void ruby_hit_callback(PacketPtr pkt); 120 void hit(PacketPtr pkt); | 112 protected: 113 const string m_name; 114 void ruby_hit_callback(PacketPtr pkt); 115 void hit(PacketPtr pkt); |
121 | 116 |
122 int m_version; 123 AbstractController* m_controller; 124 MessageBuffer* m_mandatory_q_ptr; | 117 int m_version; 118 AbstractController* m_controller; 119 MessageBuffer* m_mandatory_q_ptr; |
125 PioPort* pio_port; 126 | 120 PioPort* pio_port; 121 |
127private: | 122 private: |
128 uint16_t m_port_id; 129 uint64_t m_request_cnt; 130 131 M5Port* physMemPort; 132 133 PhysicalMemory* physmem; 134}; 135 | 123 uint16_t m_port_id; 124 uint64_t m_request_cnt; 125 126 M5Port* physMemPort; 127 128 PhysicalMemory* physmem; 129}; 130 |
136#endif | 131#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__ |