RubyPort.hh (6882:898047a3672c) RubyPort.hh (6893:9cdf9b65d946)
1
2/*
3 * Copyright (c) 2009 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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31#define RUBYPORT_H
32
33#include "mem/ruby/libruby.hh"
34#include <string>
35#include <assert.h>
36
37#include "mem/mem_object.hh"
38#include "mem/tport.hh"
1
2/*
3 * Copyright (c) 2009 Advanced Micro Devices, Inc.
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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31#define RUBYPORT_H
32
33#include "mem/ruby/libruby.hh"
34#include <string>
35#include <assert.h>
36
37#include "mem/mem_object.hh"
38#include "mem/tport.hh"
39#include "mem/physical.hh"
39
40#include "params/RubyPort.hh"
41
42using namespace std;
43
44class MessageBuffer;
45class AbstractController;
46

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58 bool sendTiming(PacketPtr pkt);
59 void hitCallback(PacketPtr pkt);
60
61 protected:
62 virtual bool recvTiming(PacketPtr pkt);
63 virtual Tick recvAtomic(PacketPtr pkt);
64
65 private:
40
41#include "params/RubyPort.hh"
42
43using namespace std;
44
45class MessageBuffer;
46class AbstractController;
47

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59 bool sendTiming(PacketPtr pkt);
60 void hitCallback(PacketPtr pkt);
61
62 protected:
63 virtual bool recvTiming(PacketPtr pkt);
64 virtual Tick recvAtomic(PacketPtr pkt);
65
66 private:
66 bool isPioAddress(Addr addr);
67 bool isPhysMemAddress(Addr addr);
68 };
69
70 friend class M5Port;
71
72 class PioPort : public SimpleTimingPort
73 {
74

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164 : pkt(p), m5Port(m5p)
165 {}
166 };
167
168 typedef std::map<int64_t, RequestCookie*> RequestMap;
169 static RequestMap pending_cpu_requests;
170 static void ruby_hit_callback(int64_t req_id);
171
67 bool isPhysMemAddress(Addr addr);
68 };
69
70 friend class M5Port;
71
72 class PioPort : public SimpleTimingPort
73 {
74

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164 : pkt(p), m5Port(m5p)
165 {}
166 };
167
168 typedef std::map<int64_t, RequestCookie*> RequestMap;
169 static RequestMap pending_cpu_requests;
170 static void ruby_hit_callback(int64_t req_id);
171
172 FunctionalPort funcMemPort;
172 M5Port* physMemPort;
173
174 PhysicalMemory* physmem;
173};
174
175#endif
175};
176
177#endif