RubyPort.hh (11308:7d8836fd043d) | RubyPort.hh (11346:64e862d3758f) |
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1/* 2 * Copyright (c) 2012-2013 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 178 unchanged lines hidden (view full) --- 187 188 RubySystem *m_ruby_system; 189 uint32_t m_version; 190 AbstractController* m_controller; 191 MessageBuffer* m_mandatory_q_ptr; 192 bool m_usingRubyTester; 193 System* system; 194 | 1/* 2 * Copyright (c) 2012-2013 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 178 unchanged lines hidden (view full) --- 187 188 RubySystem *m_ruby_system; 189 uint32_t m_version; 190 AbstractController* m_controller; 191 MessageBuffer* m_mandatory_q_ptr; 192 bool m_usingRubyTester; 193 System* system; 194 |
195 std::vector<MemSlavePort *> slave_ports; 196 |
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195 private: 196 bool onRetryList(MemSlavePort * port) 197 { 198 return (std::find(retryList.begin(), retryList.end(), port) != 199 retryList.end()); 200 } 201 void addToRetryList(MemSlavePort * port) 202 { --- 4 unchanged lines hidden (view full) --- 207 PioMasterPort pioMasterPort; 208 PioSlavePort pioSlavePort; 209 MemMasterPort memMasterPort; 210 MemSlavePort memSlavePort; 211 unsigned int gotAddrRanges; 212 213 /** Vector of M5 Ports attached to this Ruby port. */ 214 typedef std::vector<MemSlavePort *>::iterator CpuPortIter; | 197 private: 198 bool onRetryList(MemSlavePort * port) 199 { 200 return (std::find(retryList.begin(), retryList.end(), port) != 201 retryList.end()); 202 } 203 void addToRetryList(MemSlavePort * port) 204 { --- 4 unchanged lines hidden (view full) --- 209 PioMasterPort pioMasterPort; 210 PioSlavePort pioSlavePort; 211 MemMasterPort memMasterPort; 212 MemSlavePort memSlavePort; 213 unsigned int gotAddrRanges; 214 215 /** Vector of M5 Ports attached to this Ruby port. */ 216 typedef std::vector<MemSlavePort *>::iterator CpuPortIter; |
215 std::vector<MemSlavePort *> slave_ports; | |
216 std::vector<PioMasterPort *> master_ports; 217 218 // 219 // Based on similar code in the M5 bus. Stores pointers to those ports 220 // that should be called when the Sequencer becomes available after a stall. 221 // 222 std::vector<MemSlavePort *> retryList; 223 224 bool m_isCPUSequencer; 225}; 226 227#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__ | 217 std::vector<PioMasterPort *> master_ports; 218 219 // 220 // Based on similar code in the M5 bus. Stores pointers to those ports 221 // that should be called when the Sequencer becomes available after a stall. 222 // 223 std::vector<MemSlavePort *> retryList; 224 225 bool m_isCPUSequencer; 226}; 227 228#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__ |