RubyPort.hh (10467:dcf27c8220ac) RubyPort.hh (10525:77787650cbbc)
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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68 protected:
69 bool recvTimingResp(PacketPtr pkt);
70 void recvRangeChange() {}
71 };
72
73 class MemSlavePort : public QueuedSlavePort
74 {
75 private:
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 59 unchanged lines hidden (view full) ---

68 protected:
69 bool recvTimingResp(PacketPtr pkt);
70 void recvRangeChange() {}
71 };
72
73 class MemSlavePort : public QueuedSlavePort
74 {
75 private:
76
77 SlavePacketQueue queue;
78 RubySystem* ruby_system;
76 SlavePacketQueue queue;
77 RubySystem* ruby_system;
79 bool access_phys_mem;
78 bool access_backing_store;
80
81 public:
82 MemSlavePort(const std::string &_name, RubyPort *_port,
79
80 public:
81 MemSlavePort(const std::string &_name, RubyPort *_port,
83 RubySystem*_system, bool _access_phys_mem, PortID id);
82 RubySystem*_system, bool _access_backing_store, PortID id);
84 void hitCallback(PacketPtr pkt);
85 void evictionCallback(const Address& address);
86
87 protected:
88 bool recvTimingReq(PacketPtr pkt);
89
90 Tick recvAtomic(PacketPtr pkt)
91 { panic("RubyPort::MemSlavePort::recvAtomic() not implemented!\n"); }

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207
208 DrainManager *drainManager;
209
210 //
211 // Based on similar code in the M5 bus. Stores pointers to those ports
212 // that should be called when the Sequencer becomes available after a stall.
213 //
214 std::vector<MemSlavePort *> retryList;
83 void hitCallback(PacketPtr pkt);
84 void evictionCallback(const Address& address);
85
86 protected:
87 bool recvTimingReq(PacketPtr pkt);
88
89 Tick recvAtomic(PacketPtr pkt)
90 { panic("RubyPort::MemSlavePort::recvAtomic() not implemented!\n"); }

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206
207 DrainManager *drainManager;
208
209 //
210 // Based on similar code in the M5 bus. Stores pointers to those ports
211 // that should be called when the Sequencer becomes available after a stall.
212 //
213 std::vector<MemSlavePort *> retryList;
215
216 bool access_phys_mem;
217};
218
219#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__
214};
215
216#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__