RubyPort.hh (10301:44839e8febbd) RubyPort.hh (10467:dcf27c8220ac)
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 168 unchanged lines hidden (view full) ---

177 * @return Whether successfully sent
178 */
179 bool recvTimingResp(PacketPtr pkt, PortID master_port_id);
180
181 uint32_t m_version;
182 AbstractController* m_controller;
183 MessageBuffer* m_mandatory_q_ptr;
184 bool m_usingRubyTester;
1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 168 unchanged lines hidden (view full) ---

177 * @return Whether successfully sent
178 */
179 bool recvTimingResp(PacketPtr pkt, PortID master_port_id);
180
181 uint32_t m_version;
182 AbstractController* m_controller;
183 MessageBuffer* m_mandatory_q_ptr;
184 bool m_usingRubyTester;
185 System* system;
185
186 private:
187 void addToRetryList(MemSlavePort * port)
188 {
189 assert(std::find(retryList.begin(), retryList.end(), port) ==
190 retryList.end());
191 retryList.push_back(port);
192 }

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200 unsigned int gotAddrRanges;
201
202 /** Vector of M5 Ports attached to this Ruby port. */
203 typedef std::vector<MemSlavePort *>::iterator CpuPortIter;
204 std::vector<MemSlavePort *> slave_ports;
205 std::vector<PioMasterPort *> master_ports;
206
207 DrainManager *drainManager;
186
187 private:
188 void addToRetryList(MemSlavePort * port)
189 {
190 assert(std::find(retryList.begin(), retryList.end(), port) ==
191 retryList.end());
192 retryList.push_back(port);
193 }

--- 7 unchanged lines hidden (view full) ---

201 unsigned int gotAddrRanges;
202
203 /** Vector of M5 Ports attached to this Ruby port. */
204 typedef std::vector<MemSlavePort *>::iterator CpuPortIter;
205 std::vector<MemSlavePort *> slave_ports;
206 std::vector<PioMasterPort *> master_ports;
207
208 DrainManager *drainManager;
208 System* system;
209
210 //
211 // Based on similar code in the M5 bus. Stores pointers to those ports
212 // that should be called when the Sequencer becomes available after a stall.
213 //
214 std::vector<MemSlavePort *> retryList;
215
216 bool access_phys_mem;
217};
218
219#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__
209
210 //
211 // Based on similar code in the M5 bus. Stores pointers to those ports
212 // that should be called when the Sequencer becomes available after a stall.
213 //
214 std::vector<MemSlavePort *> retryList;
215
216 bool access_phys_mem;
217};
218
219#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__