RubyPort.hh (10012:ec5a5bfb941d) RubyPort.hh (10089:bc3126a05a7f)
1/*
1/*
2 * Copyright (c) 2012 ARM Limited
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

--- 49 unchanged lines hidden (view full) ---

60 public:
61 class M5Port : public QueuedSlavePort
62 {
63 private:
64
65 SlavePacketQueue queue;
66 RubyPort *ruby_port;
67 RubySystem* ruby_system;
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated

--- 49 unchanged lines hidden (view full) ---

60 public:
61 class M5Port : public QueuedSlavePort
62 {
63 private:
64
65 SlavePacketQueue queue;
66 RubyPort *ruby_port;
67 RubySystem* ruby_system;
68 bool _onRetryList;
69 bool access_phys_mem;
70
71 public:
72 M5Port(const std::string &_name, RubyPort *_port,
68 bool access_phys_mem;
69
70 public:
71 M5Port(const std::string &_name, RubyPort *_port,
73 RubySystem*_system, bool _access_phys_mem);
72 RubySystem*_system, bool _access_phys_mem, PortID id);
74 void hitCallback(PacketPtr pkt);
75 void evictionCallback(const Address& address);
73 void hitCallback(PacketPtr pkt);
74 void evictionCallback(const Address& address);
76
77 bool onRetryList()
78 { return _onRetryList; }
79
80 void onRetryList(bool newVal)
81 { _onRetryList = newVal; }
82
83 protected:
75
76 protected:
84 virtual bool recvTimingReq(PacketPtr pkt);
85 virtual Tick recvAtomic(PacketPtr pkt);
86 virtual void recvFunctional(PacketPtr pkt);
87 virtual AddrRangeList getAddrRanges() const;
77 bool recvTimingReq(PacketPtr pkt);
78 Tick recvAtomic(PacketPtr pkt);
79 void recvFunctional(PacketPtr pkt);
80 AddrRangeList getAddrRanges() const;
88
89 private:
81
82 private:
90 bool isPhysMemAddress(Addr addr);
83 bool isPhysMemAddress(Addr addr) const;
91 };
92
84 };
85
93 friend class M5Port;
94
95 class PioPort : public QueuedMasterPort
96 {
97 private:
98
99 MasterPacketQueue queue;
86 class PioPort : public QueuedMasterPort
87 {
88 private:
89
90 MasterPacketQueue queue;
91 RubyPort *ruby_port;
100
101 public:
102 PioPort(const std::string &_name, RubyPort *_port);
103
104 protected:
92
93 public:
94 PioPort(const std::string &_name, RubyPort *_port);
95
96 protected:
105 virtual bool recvTimingResp(PacketPtr pkt);
97 bool recvTimingResp(PacketPtr pkt)
98 { return ruby_port->recvTimingResp(pkt, id); }
106 };
107
99 };
100
108 friend class PioPort;
109
110 struct SenderState : public Packet::SenderState
111 {
112 M5Port* port;
113
114 SenderState(M5Port* _port) : port(_port)
115 {}
116 };
117
118 typedef RubyPortParams Params;
119 RubyPort(const Params *p);
120 virtual ~RubyPort() {}
121
122 void init();
123
124 BaseMasterPort &getMasterPort(const std::string &if_name,
125 PortID idx = InvalidPortID);

--- 14 unchanged lines hidden (view full) ---

140 unsigned int drain(DrainManager *dm);
141
142 protected:
143 const std::string m_name;
144 void ruby_hit_callback(PacketPtr pkt);
145 void testDrainComplete();
146 void ruby_eviction_callback(const Address& address);
147
101 typedef RubyPortParams Params;
102 RubyPort(const Params *p);
103 virtual ~RubyPort() {}
104
105 void init();
106
107 BaseMasterPort &getMasterPort(const std::string &if_name,
108 PortID idx = InvalidPortID);

--- 14 unchanged lines hidden (view full) ---

123 unsigned int drain(DrainManager *dm);
124
125 protected:
126 const std::string m_name;
127 void ruby_hit_callback(PacketPtr pkt);
128 void testDrainComplete();
129 void ruby_eviction_callback(const Address& address);
130
131 /**
132 * Called by the PIO port when receiving a timing response.
133 *
134 * @param pkt Response packet
135 * @param master_port_id Port id of the PIO port
136 *
137 * @return Whether successfully sent
138 */
139 bool recvTimingResp(PacketPtr pkt, PortID master_port_id);
140
148 uint32_t m_version;
149 AbstractController* m_controller;
150 MessageBuffer* m_mandatory_q_ptr;
151 PioPort pio_port;
152 bool m_usingRubyTester;
153
154 private:
155 void addToRetryList(M5Port * port)
156 {
141 uint32_t m_version;
142 AbstractController* m_controller;
143 MessageBuffer* m_mandatory_q_ptr;
144 PioPort pio_port;
145 bool m_usingRubyTester;
146
147 private:
148 void addToRetryList(M5Port * port)
149 {
157 if (!port->onRetryList()) {
158 port->onRetryList(true);
159 retryList.push_back(port);
160 waitingOnSequencer = true;
161 }
150 assert(std::find(retryList.begin(), retryList.end(), port) ==
151 retryList.end());
152 retryList.push_back(port);
162 }
163
164 unsigned int getChildDrainCount(DrainManager *dm);
165
153 }
154
155 unsigned int getChildDrainCount(DrainManager *dm);
156
166 uint16_t m_port_id;
167 uint64_t m_request_cnt;
168
169 /** Vector of M5 Ports attached to this Ruby port. */
170 typedef std::vector<M5Port*>::iterator CpuPortIter;
171 std::vector<M5Port*> slave_ports;
172 std::vector<PioPort*> master_ports;
173
174 DrainManager *drainManager;
175
176 RubySystem* ruby_system;
177 System* system;
178
179 //
180 // Based on similar code in the M5 bus. Stores pointers to those ports
181 // that should be called when the Sequencer becomes available after a stall.
182 //
157 /** Vector of M5 Ports attached to this Ruby port. */
158 typedef std::vector<M5Port*>::iterator CpuPortIter;
159 std::vector<M5Port*> slave_ports;
160 std::vector<PioPort*> master_ports;
161
162 DrainManager *drainManager;
163
164 RubySystem* ruby_system;
165 System* system;
166
167 //
168 // Based on similar code in the M5 bus. Stores pointers to those ports
169 // that should be called when the Sequencer becomes available after a stall.
170 //
183 std::list<M5Port*> retryList;
171 std::vector<M5Port*> retryList;
184
172
185 bool waitingOnSequencer;
186 bool access_phys_mem;
187};
188
189#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__
173 bool access_phys_mem;
174};
175
176#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__