1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * 14 * Copyright (c) 2009 Advanced Micro Devices, Inc. 15 * Copyright (c) 2011 Mark D. Hill and David A. Wood 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution; 25 * neither the name of the copyright holders nor the names of its 26 * contributors may be used to endorse or promote products derived from 27 * this software without specific prior written permission. 28 * 29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40 */ 41 42#ifndef __MEM_RUBY_SYSTEM_RUBYPORT_HH__ 43#define __MEM_RUBY_SYSTEM_RUBYPORT_HH__ 44 45#include <cassert> 46#include <string> 47 48#include "mem/protocol/RequestStatus.hh" 49#include "mem/ruby/buffers/MessageBuffer.hh" 50#include "mem/ruby/system/System.hh" 51#include "mem/mem_object.hh" 52#include "mem/physical.hh" 53#include "mem/tport.hh" 54#include "params/RubyPort.hh" 55 56class AbstractController; 57 58class RubyPort : public MemObject 59{ 60 public: 61 class M5Port : public QueuedSlavePort 62 { 63 private: 64 65 SlavePacketQueue queue; 66 RubyPort *ruby_port; 67 RubySystem* ruby_system; 68 bool _onRetryList; 69 bool access_phys_mem; 70 71 public: 72 M5Port(const std::string &_name, RubyPort *_port, 73 RubySystem*_system, bool _access_phys_mem); 74 void hitCallback(PacketPtr pkt); 75 void evictionCallback(const Address& address); 76 unsigned deviceBlockSize() const; 77 78 bool onRetryList() 79 { return _onRetryList; } 80 81 void onRetryList(bool newVal) 82 { _onRetryList = newVal; } 83 84 protected: 85 virtual bool recvTimingReq(PacketPtr pkt); 86 virtual Tick recvAtomic(PacketPtr pkt); 87 virtual void recvFunctional(PacketPtr pkt); 88 virtual AddrRangeList getAddrRanges() const; 89 90 private: 91 bool isPhysMemAddress(Addr addr); 92 }; 93 94 friend class M5Port; 95 96 class PioPort : public QueuedMasterPort 97 { 98 private: 99 100 MasterPacketQueue queue; 101 |
102 public: 103 PioPort(const std::string &_name, RubyPort *_port); 104 105 protected: 106 virtual bool recvTimingResp(PacketPtr pkt); 107 }; 108 109 friend class PioPort; 110 111 struct SenderState : public Packet::SenderState 112 { 113 M5Port* port; 114 115 SenderState(M5Port* _port) : port(_port) 116 {} 117 }; 118 119 typedef RubyPortParams Params; 120 RubyPort(const Params *p); 121 virtual ~RubyPort() {} 122 123 void init(); 124 125 BaseMasterPort &getMasterPort(const std::string &if_name, 126 PortID idx = InvalidPortID); 127 BaseSlavePort &getSlavePort(const std::string &if_name, 128 PortID idx = InvalidPortID); 129 130 virtual RequestStatus makeRequest(PacketPtr pkt) = 0; 131 virtual int outstandingCount() const = 0; 132 virtual bool isDeadlockEventScheduled() const = 0; 133 virtual void descheduleDeadlockEvent() = 0; 134 135 // 136 // Called by the controller to give the sequencer a pointer. 137 // A pointer to the controller is needed for atomic support. 138 // 139 void setController(AbstractController* _cntrl) { m_controller = _cntrl; } 140 int getId() { return m_version; } 141 unsigned int drain(DrainManager *dm); 142 143 protected: 144 const std::string m_name; 145 void ruby_hit_callback(PacketPtr pkt); 146 void testDrainComplete(); 147 void ruby_eviction_callback(const Address& address); 148 149 int m_version; 150 AbstractController* m_controller; 151 MessageBuffer* m_mandatory_q_ptr; 152 PioPort pio_port; 153 bool m_usingRubyTester; 154 155 private: 156 void addToRetryList(M5Port * port) 157 { 158 if (!port->onRetryList()) { 159 port->onRetryList(true); 160 retryList.push_back(port); 161 waitingOnSequencer = true; 162 } 163 } 164 165 unsigned int getChildDrainCount(DrainManager *dm); 166 167 uint16_t m_port_id; 168 uint64_t m_request_cnt; 169 170 /** Vector of M5 Ports attached to this Ruby port. */ 171 typedef std::vector<M5Port*>::iterator CpuPortIter; 172 std::vector<M5Port*> slave_ports; 173 std::vector<PioPort*> master_ports; 174 175 DrainManager *drainManager; 176 177 RubySystem* ruby_system; 178 System* system; 179 180 // 181 // Based on similar code in the M5 bus. Stores pointers to those ports 182 // that should be called when the Sequencer becomes available after a stall. 183 // 184 std::list<M5Port*> retryList; 185 186 bool waitingOnSequencer; 187 bool access_phys_mem; 188}; 189 190#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__ |