1/* 2 * Copyright (c) 2012-2013 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software 9 * licensed hereunder. You may use the software subject to the license 10 * terms below provided that you ensure that this notice is replicated 11 * unmodified and in its entirety in all distributions of the software, 12 * modified or unmodified, in source code or in binary form. 13 * |
14 * Copyright (c) 2009-2013 Advanced Micro Devices, Inc. |
15 * Copyright (c) 2011 Mark D. Hill and David A. Wood 16 * All rights reserved. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions are 20 * met: redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer; 22 * redistributions in binary form must reproduce the above copyright --- 48 unchanged lines hidden (view full) --- 71 void recvRangeChange() {} 72 }; 73 74 class MemSlavePort : public QueuedSlavePort 75 { 76 private: 77 RespPacketQueue queue; 78 bool access_backing_store; |
79 bool no_retry_on_stall; |
80 81 public: 82 MemSlavePort(const std::string &_name, RubyPort *_port, |
83 bool _access_backing_store, 84 PortID id, bool _no_retry_on_stall); |
85 void hitCallback(PacketPtr pkt); 86 void evictionCallback(Addr address); 87 88 protected: 89 bool recvTimingReq(PacketPtr pkt); 90 91 Tick recvAtomic(PacketPtr pkt) 92 { panic("RubyPort::MemSlavePort::recvAtomic() not implemented!\n"); } 93 94 void recvFunctional(PacketPtr pkt); 95 96 AddrRangeList getAddrRanges() const 97 { AddrRangeList ranges; return ranges; } 98 |
99 void addToRetryList(); 100 |
101 private: 102 bool isPhysMemAddress(Addr addr) const; 103 }; 104 105 class PioMasterPort : public QueuedMasterPort 106 { 107 private: 108 ReqPacketQueue reqQueue; --- 54 unchanged lines hidden (view full) --- 163 // Called by the controller to give the sequencer a pointer. 164 // A pointer to the controller is needed for atomic support. 165 // 166 void setController(AbstractController* _cntrl) { m_controller = _cntrl; } 167 uint32_t getId() { return m_version; } 168 DrainState drain() override; 169 170 protected: |
171 void trySendRetries(); |
172 void ruby_hit_callback(PacketPtr pkt); 173 void testDrainComplete(); 174 void ruby_eviction_callback(Addr address); 175 176 /** 177 * Called by the PIO port when receiving a timing response. 178 * 179 * @param pkt Response packet --- 6 unchanged lines hidden (view full) --- 186 RubySystem *m_ruby_system; 187 uint32_t m_version; 188 AbstractController* m_controller; 189 MessageBuffer* m_mandatory_q_ptr; 190 bool m_usingRubyTester; 191 System* system; 192 193 private: |
194 bool onRetryList(MemSlavePort * port) 195 { 196 return (std::find(retryList.begin(), retryList.end(), port) != 197 retryList.end()); 198 } |
199 void addToRetryList(MemSlavePort * port) 200 { |
201 if (onRetryList(port)) return; |
202 retryList.push_back(port); 203 } 204 205 PioMasterPort pioMasterPort; 206 PioSlavePort pioSlavePort; 207 MemMasterPort memMasterPort; 208 MemSlavePort memSlavePort; 209 unsigned int gotAddrRanges; --- 14 unchanged lines hidden --- |