1/* 2 * Copyright (c) 2012-2013 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 59 unchanged lines hidden (view full) --- 68 protected: 69 bool recvTimingResp(PacketPtr pkt); 70 void recvRangeChange() {} 71 }; 72 73 class MemSlavePort : public QueuedSlavePort 74 { 75 private: |
76 SlavePacketQueue queue; 77 RubySystem* ruby_system; |
78 bool access_backing_store; |
79 80 public: 81 MemSlavePort(const std::string &_name, RubyPort *_port, |
82 RubySystem*_system, bool _access_backing_store, PortID id); |
83 void hitCallback(PacketPtr pkt); 84 void evictionCallback(const Address& address); 85 86 protected: 87 bool recvTimingReq(PacketPtr pkt); 88 89 Tick recvAtomic(PacketPtr pkt) 90 { panic("RubyPort::MemSlavePort::recvAtomic() not implemented!\n"); } --- 115 unchanged lines hidden (view full) --- 206 207 DrainManager *drainManager; 208 209 // 210 // Based on similar code in the M5 bus. Stores pointers to those ports 211 // that should be called when the Sequencer becomes available after a stall. 212 // 213 std::vector<MemSlavePort *> retryList; |
214}; 215 216#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__ |