1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009-2013 Advanced Micro Devices, Inc.
15 * Copyright (c) 2011 Mark D. Hill and David A. Wood
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
42#ifndef __MEM_RUBY_SYSTEM_RUBYPORT_HH__
43#define __MEM_RUBY_SYSTEM_RUBYPORT_HH__
44
45#include <cassert>
46#include <string>
47
48#include "mem/protocol/RequestStatus.hh"
| 1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009-2013 Advanced Micro Devices, Inc.
15 * Copyright (c) 2011 Mark D. Hill and David A. Wood
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
42#ifndef __MEM_RUBY_SYSTEM_RUBYPORT_HH__
43#define __MEM_RUBY_SYSTEM_RUBYPORT_HH__
44
45#include <cassert>
46#include <string>
47
48#include "mem/protocol/RequestStatus.hh"
|
| 49#include "mem/ruby/common/MachineID.hh"
|
49#include "mem/ruby/network/MessageBuffer.hh"
50#include "mem/ruby/system/RubySystem.hh"
51#include "mem/mem_object.hh"
52#include "mem/tport.hh"
53#include "params/RubyPort.hh"
54
55class AbstractController;
56
57class RubyPort : public MemObject
58{
59 public:
60 class MemMasterPort : public QueuedMasterPort
61 {
62 private:
63 ReqPacketQueue reqQueue;
64 SnoopRespPacketQueue snoopRespQueue;
65
66 public:
67 MemMasterPort(const std::string &_name, RubyPort *_port);
68
69 protected:
70 bool recvTimingResp(PacketPtr pkt);
71 void recvRangeChange() {}
72 };
73
74 class MemSlavePort : public QueuedSlavePort
75 {
76 private:
77 RespPacketQueue queue;
78 bool access_backing_store;
79 bool no_retry_on_stall;
80
81 public:
82 MemSlavePort(const std::string &_name, RubyPort *_port,
83 bool _access_backing_store,
84 PortID id, bool _no_retry_on_stall);
85 void hitCallback(PacketPtr pkt);
86 void evictionCallback(Addr address);
87
88 protected:
89 bool recvTimingReq(PacketPtr pkt);
90
| 50#include "mem/ruby/network/MessageBuffer.hh"
51#include "mem/ruby/system/RubySystem.hh"
52#include "mem/mem_object.hh"
53#include "mem/tport.hh"
54#include "params/RubyPort.hh"
55
56class AbstractController;
57
58class RubyPort : public MemObject
59{
60 public:
61 class MemMasterPort : public QueuedMasterPort
62 {
63 private:
64 ReqPacketQueue reqQueue;
65 SnoopRespPacketQueue snoopRespQueue;
66
67 public:
68 MemMasterPort(const std::string &_name, RubyPort *_port);
69
70 protected:
71 bool recvTimingResp(PacketPtr pkt);
72 void recvRangeChange() {}
73 };
74
75 class MemSlavePort : public QueuedSlavePort
76 {
77 private:
78 RespPacketQueue queue;
79 bool access_backing_store;
80 bool no_retry_on_stall;
81
82 public:
83 MemSlavePort(const std::string &_name, RubyPort *_port,
84 bool _access_backing_store,
85 PortID id, bool _no_retry_on_stall);
86 void hitCallback(PacketPtr pkt);
87 void evictionCallback(Addr address);
88
89 protected:
90 bool recvTimingReq(PacketPtr pkt);
91
|
91 Tick recvAtomic(PacketPtr pkt)
92 { panic("RubyPort::MemSlavePort::recvAtomic() not implemented!\n"); }
| 92 Tick recvAtomic(PacketPtr pkt);
|
93
94 void recvFunctional(PacketPtr pkt);
95
96 AddrRangeList getAddrRanges() const
97 { AddrRangeList ranges; return ranges; }
98
99 void addToRetryList();
100
101 private:
102 bool isPhysMemAddress(Addr addr) const;
103 };
104
105 class PioMasterPort : public QueuedMasterPort
106 {
107 private:
108 ReqPacketQueue reqQueue;
109 SnoopRespPacketQueue snoopRespQueue;
110
111 public:
112 PioMasterPort(const std::string &_name, RubyPort *_port);
113
114 protected:
115 bool recvTimingResp(PacketPtr pkt);
116 void recvRangeChange();
117 };
118
119 class PioSlavePort : public QueuedSlavePort
120 {
121 private:
122 RespPacketQueue queue;
123
124 public:
125 PioSlavePort(const std::string &_name, RubyPort *_port);
126
127 protected:
128 bool recvTimingReq(PacketPtr pkt);
129
| 93
94 void recvFunctional(PacketPtr pkt);
95
96 AddrRangeList getAddrRanges() const
97 { AddrRangeList ranges; return ranges; }
98
99 void addToRetryList();
100
101 private:
102 bool isPhysMemAddress(Addr addr) const;
103 };
104
105 class PioMasterPort : public QueuedMasterPort
106 {
107 private:
108 ReqPacketQueue reqQueue;
109 SnoopRespPacketQueue snoopRespQueue;
110
111 public:
112 PioMasterPort(const std::string &_name, RubyPort *_port);
113
114 protected:
115 bool recvTimingResp(PacketPtr pkt);
116 void recvRangeChange();
117 };
118
119 class PioSlavePort : public QueuedSlavePort
120 {
121 private:
122 RespPacketQueue queue;
123
124 public:
125 PioSlavePort(const std::string &_name, RubyPort *_port);
126
127 protected:
128 bool recvTimingReq(PacketPtr pkt);
129
|
130 Tick recvAtomic(PacketPtr pkt)
131 { panic("recvAtomic not supported with ruby!"); }
| 130 Tick recvAtomic(PacketPtr pkt);
|
132
133 void recvFunctional(PacketPtr pkt)
134 { panic("recvFunctional should never be called on pio slave port!"); }
135
136 AddrRangeList getAddrRanges() const;
137 };
138
139 struct SenderState : public Packet::SenderState
140 {
141 MemSlavePort *port;
142 SenderState(MemSlavePort * _port) : port(_port)
143 {}
144 };
145
146 typedef RubyPortParams Params;
147 RubyPort(const Params *p);
148 virtual ~RubyPort() {}
149
150 void init() override;
151
152 BaseMasterPort &getMasterPort(const std::string &if_name,
153 PortID idx = InvalidPortID) override;
154 BaseSlavePort &getSlavePort(const std::string &if_name,
155 PortID idx = InvalidPortID) override;
156
157 virtual RequestStatus makeRequest(PacketPtr pkt) = 0;
158 virtual int outstandingCount() const = 0;
159 virtual bool isDeadlockEventScheduled() const = 0;
160 virtual void descheduleDeadlockEvent() = 0;
161
162 //
163 // Called by the controller to give the sequencer a pointer.
164 // A pointer to the controller is needed for atomic support.
165 //
166 void setController(AbstractController* _cntrl) { m_controller = _cntrl; }
167 uint32_t getId() { return m_version; }
168 DrainState drain() override;
169
170 bool isCPUSequencer() { return m_isCPUSequencer; }
171
172 protected:
173 void trySendRetries();
174 void ruby_hit_callback(PacketPtr pkt);
175 void testDrainComplete();
176 void ruby_eviction_callback(Addr address);
177
178 /**
179 * Called by the PIO port when receiving a timing response.
180 *
181 * @param pkt Response packet
182 * @param master_port_id Port id of the PIO port
183 *
184 * @return Whether successfully sent
185 */
186 bool recvTimingResp(PacketPtr pkt, PortID master_port_id);
187
188 RubySystem *m_ruby_system;
189 uint32_t m_version;
190 AbstractController* m_controller;
191 MessageBuffer* m_mandatory_q_ptr;
192 bool m_usingRubyTester;
193 System* system;
194
195 std::vector<MemSlavePort *> slave_ports;
196
197 private:
198 bool onRetryList(MemSlavePort * port)
199 {
200 return (std::find(retryList.begin(), retryList.end(), port) !=
201 retryList.end());
202 }
203 void addToRetryList(MemSlavePort * port)
204 {
205 if (onRetryList(port)) return;
206 retryList.push_back(port);
207 }
208
209 PioMasterPort pioMasterPort;
210 PioSlavePort pioSlavePort;
211 MemMasterPort memMasterPort;
212 MemSlavePort memSlavePort;
213 unsigned int gotAddrRanges;
214
215 /** Vector of M5 Ports attached to this Ruby port. */
216 typedef std::vector<MemSlavePort *>::iterator CpuPortIter;
217 std::vector<PioMasterPort *> master_ports;
218
219 //
220 // Based on similar code in the M5 bus. Stores pointers to those ports
221 // that should be called when the Sequencer becomes available after a stall.
222 //
223 std::vector<MemSlavePort *> retryList;
224
225 bool m_isCPUSequencer;
226};
227
228#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__
| 131
132 void recvFunctional(PacketPtr pkt)
133 { panic("recvFunctional should never be called on pio slave port!"); }
134
135 AddrRangeList getAddrRanges() const;
136 };
137
138 struct SenderState : public Packet::SenderState
139 {
140 MemSlavePort *port;
141 SenderState(MemSlavePort * _port) : port(_port)
142 {}
143 };
144
145 typedef RubyPortParams Params;
146 RubyPort(const Params *p);
147 virtual ~RubyPort() {}
148
149 void init() override;
150
151 BaseMasterPort &getMasterPort(const std::string &if_name,
152 PortID idx = InvalidPortID) override;
153 BaseSlavePort &getSlavePort(const std::string &if_name,
154 PortID idx = InvalidPortID) override;
155
156 virtual RequestStatus makeRequest(PacketPtr pkt) = 0;
157 virtual int outstandingCount() const = 0;
158 virtual bool isDeadlockEventScheduled() const = 0;
159 virtual void descheduleDeadlockEvent() = 0;
160
161 //
162 // Called by the controller to give the sequencer a pointer.
163 // A pointer to the controller is needed for atomic support.
164 //
165 void setController(AbstractController* _cntrl) { m_controller = _cntrl; }
166 uint32_t getId() { return m_version; }
167 DrainState drain() override;
168
169 bool isCPUSequencer() { return m_isCPUSequencer; }
170
171 protected:
172 void trySendRetries();
173 void ruby_hit_callback(PacketPtr pkt);
174 void testDrainComplete();
175 void ruby_eviction_callback(Addr address);
176
177 /**
178 * Called by the PIO port when receiving a timing response.
179 *
180 * @param pkt Response packet
181 * @param master_port_id Port id of the PIO port
182 *
183 * @return Whether successfully sent
184 */
185 bool recvTimingResp(PacketPtr pkt, PortID master_port_id);
186
187 RubySystem *m_ruby_system;
188 uint32_t m_version;
189 AbstractController* m_controller;
190 MessageBuffer* m_mandatory_q_ptr;
191 bool m_usingRubyTester;
192 System* system;
193
194 std::vector<MemSlavePort *> slave_ports;
195
196 private:
197 bool onRetryList(MemSlavePort * port)
198 {
199 return (std::find(retryList.begin(), retryList.end(), port) !=
200 retryList.end());
201 }
202 void addToRetryList(MemSlavePort * port)
203 {
204 if (onRetryList(port)) return;
205 retryList.push_back(port);
206 }
207
208 PioMasterPort pioMasterPort;
209 PioSlavePort pioSlavePort;
210 MemMasterPort memMasterPort;
211 MemSlavePort memSlavePort;
212 unsigned int gotAddrRanges;
213
214 /** Vector of M5 Ports attached to this Ruby port. */
215 typedef std::vector<MemSlavePort *>::iterator CpuPortIter;
216 std::vector<PioMasterPort *> master_ports;
217
218 //
219 // Based on similar code in the M5 bus. Stores pointers to those ports
220 // that should be called when the Sequencer becomes available after a stall.
221 //
222 std::vector<MemSlavePort *> retryList;
223
224 bool m_isCPUSequencer;
225};
226
227#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__
|