1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 Advanced Micro Devices, Inc.
15 * Copyright (c) 2011 Mark D. Hill and David A. Wood
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
42#ifndef __MEM_RUBY_SYSTEM_RUBYPORT_HH__
43#define __MEM_RUBY_SYSTEM_RUBYPORT_HH__
44
45#include <cassert>
46#include <string>
47
48#include "mem/protocol/RequestStatus.hh"
49#include "mem/ruby/network/MessageBuffer.hh"
50#include "mem/ruby/system/System.hh"
51#include "mem/mem_object.hh"
52#include "mem/tport.hh"
53#include "params/RubyPort.hh"
54
55class AbstractController;
56
57class RubyPort : public MemObject
58{
59 public:
60 class MemMasterPort : public QueuedMasterPort
61 {
62 private:
63 MasterPacketQueue queue;
64
65 public:
66 MemMasterPort(const std::string &_name, RubyPort *_port);
67
68 protected:
69 bool recvTimingResp(PacketPtr pkt);
70 void recvRangeChange() {}
71 };
72
73 class MemSlavePort : public QueuedSlavePort
74 {
75 private:
76
77 SlavePacketQueue queue;
78 RubySystem* ruby_system;
79 bool access_phys_mem;
80
81 public:
82 MemSlavePort(const std::string &_name, RubyPort *_port,
83 RubySystem*_system, bool _access_phys_mem, PortID id);
84 void hitCallback(PacketPtr pkt);
85 void evictionCallback(const Address& address);
86
87 protected:
88 bool recvTimingReq(PacketPtr pkt);
89
90 Tick recvAtomic(PacketPtr pkt)
91 { panic("RubyPort::MemSlavePort::recvAtomic() not implemented!\n"); }
92
93 void recvFunctional(PacketPtr pkt);
94
95 AddrRangeList getAddrRanges() const
96 { AddrRangeList ranges; return ranges; }
97
98 private:
99 bool isPhysMemAddress(Addr addr) const;
100 };
101
102 class PioMasterPort : public QueuedMasterPort
103 {
104 private:
105 MasterPacketQueue queue;
106
107 public:
108 PioMasterPort(const std::string &_name, RubyPort *_port);
109
110 protected:
111 bool recvTimingResp(PacketPtr pkt);
112 void recvRangeChange();
113 };
114
115 class PioSlavePort : public QueuedSlavePort
116 {
117 private:
118 SlavePacketQueue queue;
119
120 public:
121 PioSlavePort(const std::string &_name, RubyPort *_port);
122
123 protected:
124 bool recvTimingReq(PacketPtr pkt);
125
126 Tick recvAtomic(PacketPtr pkt)
127 { panic("recvAtomic not supported with ruby!"); }
128
129 void recvFunctional(PacketPtr pkt)
130 { panic("recvFunctional should never be called on pio slave port!"); }
131
132 AddrRangeList getAddrRanges() const;
133 };
134
135 struct SenderState : public Packet::SenderState
136 {
137 MemSlavePort *port;
138 SenderState(MemSlavePort * _port) : port(_port)
139 {}
140 };
141
142 typedef RubyPortParams Params;
143 RubyPort(const Params *p);
144 virtual ~RubyPort() {}
145
146 void init();
147
148 BaseMasterPort &getMasterPort(const std::string &if_name,
149 PortID idx = InvalidPortID);
150 BaseSlavePort &getSlavePort(const std::string &if_name,
151 PortID idx = InvalidPortID);
152
153 virtual RequestStatus makeRequest(PacketPtr pkt) = 0;
154 virtual int outstandingCount() const = 0;
155 virtual bool isDeadlockEventScheduled() const = 0;
156 virtual void descheduleDeadlockEvent() = 0;
157
158 //
159 // Called by the controller to give the sequencer a pointer.
160 // A pointer to the controller is needed for atomic support.
161 //
162 void setController(AbstractController* _cntrl) { m_controller = _cntrl; }
163 uint32_t getId() { return m_version; }
164 unsigned int drain(DrainManager *dm);
165
166 protected:
167 void ruby_hit_callback(PacketPtr pkt);
168 void testDrainComplete();
169 void ruby_eviction_callback(const Address& address);
170
171 /**
172 * Called by the PIO port when receiving a timing response.
173 *
174 * @param pkt Response packet
175 * @param master_port_id Port id of the PIO port
176 *
177 * @return Whether successfully sent
178 */
179 bool recvTimingResp(PacketPtr pkt, PortID master_port_id);
180
181 uint32_t m_version;
182 AbstractController* m_controller;
183 MessageBuffer* m_mandatory_q_ptr;
184 bool m_usingRubyTester;
| 1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 Advanced Micro Devices, Inc.
15 * Copyright (c) 2011 Mark D. Hill and David A. Wood
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
42#ifndef __MEM_RUBY_SYSTEM_RUBYPORT_HH__
43#define __MEM_RUBY_SYSTEM_RUBYPORT_HH__
44
45#include <cassert>
46#include <string>
47
48#include "mem/protocol/RequestStatus.hh"
49#include "mem/ruby/network/MessageBuffer.hh"
50#include "mem/ruby/system/System.hh"
51#include "mem/mem_object.hh"
52#include "mem/tport.hh"
53#include "params/RubyPort.hh"
54
55class AbstractController;
56
57class RubyPort : public MemObject
58{
59 public:
60 class MemMasterPort : public QueuedMasterPort
61 {
62 private:
63 MasterPacketQueue queue;
64
65 public:
66 MemMasterPort(const std::string &_name, RubyPort *_port);
67
68 protected:
69 bool recvTimingResp(PacketPtr pkt);
70 void recvRangeChange() {}
71 };
72
73 class MemSlavePort : public QueuedSlavePort
74 {
75 private:
76
77 SlavePacketQueue queue;
78 RubySystem* ruby_system;
79 bool access_phys_mem;
80
81 public:
82 MemSlavePort(const std::string &_name, RubyPort *_port,
83 RubySystem*_system, bool _access_phys_mem, PortID id);
84 void hitCallback(PacketPtr pkt);
85 void evictionCallback(const Address& address);
86
87 protected:
88 bool recvTimingReq(PacketPtr pkt);
89
90 Tick recvAtomic(PacketPtr pkt)
91 { panic("RubyPort::MemSlavePort::recvAtomic() not implemented!\n"); }
92
93 void recvFunctional(PacketPtr pkt);
94
95 AddrRangeList getAddrRanges() const
96 { AddrRangeList ranges; return ranges; }
97
98 private:
99 bool isPhysMemAddress(Addr addr) const;
100 };
101
102 class PioMasterPort : public QueuedMasterPort
103 {
104 private:
105 MasterPacketQueue queue;
106
107 public:
108 PioMasterPort(const std::string &_name, RubyPort *_port);
109
110 protected:
111 bool recvTimingResp(PacketPtr pkt);
112 void recvRangeChange();
113 };
114
115 class PioSlavePort : public QueuedSlavePort
116 {
117 private:
118 SlavePacketQueue queue;
119
120 public:
121 PioSlavePort(const std::string &_name, RubyPort *_port);
122
123 protected:
124 bool recvTimingReq(PacketPtr pkt);
125
126 Tick recvAtomic(PacketPtr pkt)
127 { panic("recvAtomic not supported with ruby!"); }
128
129 void recvFunctional(PacketPtr pkt)
130 { panic("recvFunctional should never be called on pio slave port!"); }
131
132 AddrRangeList getAddrRanges() const;
133 };
134
135 struct SenderState : public Packet::SenderState
136 {
137 MemSlavePort *port;
138 SenderState(MemSlavePort * _port) : port(_port)
139 {}
140 };
141
142 typedef RubyPortParams Params;
143 RubyPort(const Params *p);
144 virtual ~RubyPort() {}
145
146 void init();
147
148 BaseMasterPort &getMasterPort(const std::string &if_name,
149 PortID idx = InvalidPortID);
150 BaseSlavePort &getSlavePort(const std::string &if_name,
151 PortID idx = InvalidPortID);
152
153 virtual RequestStatus makeRequest(PacketPtr pkt) = 0;
154 virtual int outstandingCount() const = 0;
155 virtual bool isDeadlockEventScheduled() const = 0;
156 virtual void descheduleDeadlockEvent() = 0;
157
158 //
159 // Called by the controller to give the sequencer a pointer.
160 // A pointer to the controller is needed for atomic support.
161 //
162 void setController(AbstractController* _cntrl) { m_controller = _cntrl; }
163 uint32_t getId() { return m_version; }
164 unsigned int drain(DrainManager *dm);
165
166 protected:
167 void ruby_hit_callback(PacketPtr pkt);
168 void testDrainComplete();
169 void ruby_eviction_callback(const Address& address);
170
171 /**
172 * Called by the PIO port when receiving a timing response.
173 *
174 * @param pkt Response packet
175 * @param master_port_id Port id of the PIO port
176 *
177 * @return Whether successfully sent
178 */
179 bool recvTimingResp(PacketPtr pkt, PortID master_port_id);
180
181 uint32_t m_version;
182 AbstractController* m_controller;
183 MessageBuffer* m_mandatory_q_ptr;
184 bool m_usingRubyTester;
|