1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 Advanced Micro Devices, Inc.
15 * Copyright (c) 2011 Mark D. Hill and David A. Wood
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
42#ifndef __MEM_RUBY_SYSTEM_RUBYPORT_HH__
43#define __MEM_RUBY_SYSTEM_RUBYPORT_HH__
44
45#include <cassert>
46#include <string>
47
48#include "mem/protocol/RequestStatus.hh"
49#include "mem/ruby/system/System.hh"
50#include "mem/mem_object.hh"
51#include "mem/physical.hh"
52#include "mem/tport.hh"
53#include "params/RubyPort.hh"
54
55class MessageBuffer;
56class AbstractController;
57
58class RubyPort : public MemObject
59{
60 public:
61 class M5Port : public QueuedSlavePort
62 {
63 private:
64
65 PacketQueue queue;
66 RubyPort *ruby_port;
67 RubySystem* ruby_system;
68 bool _onRetryList;
69 bool access_phys_mem;
70
71 public:
72 M5Port(const std::string &_name, RubyPort *_port,
73 RubySystem*_system, bool _access_phys_mem);
74 bool sendNextCycle(PacketPtr pkt);
75 void hitCallback(PacketPtr pkt);
76 void evictionCallback(const Address& address);
77 unsigned deviceBlockSize() const;
78
79 bool onRetryList()
80 { return _onRetryList; }
81
82 void onRetryList(bool newVal)
83 { _onRetryList = newVal; }
84
85 protected:
86 virtual bool recvTiming(PacketPtr pkt);
87 virtual Tick recvAtomic(PacketPtr pkt);
88 virtual void recvFunctional(PacketPtr pkt);
89 virtual AddrRangeList getAddrRanges();
90
91 private:
92 bool isPhysMemAddress(Addr addr);
93 bool doFunctionalRead(PacketPtr pkt);
94 bool doFunctionalWrite(PacketPtr pkt);
95 };
96
97 friend class M5Port;
98
99 class PioPort : public QueuedMasterPort
100 {
101 private:
102
103 PacketQueue queue;
104
105 RubyPort *ruby_port;
106
107 public:
108 PioPort(const std::string &_name, RubyPort *_port);
109 bool sendNextCycle(PacketPtr pkt);
110
111 protected:
112 virtual bool recvTiming(PacketPtr pkt);
113 virtual Tick recvAtomic(PacketPtr pkt);
114 virtual void recvFunctional(PacketPtr pkt) { }
115 };
116
117 friend class PioPort;
118
119 struct SenderState : public Packet::SenderState
120 {
121 M5Port* port;
122 Packet::SenderState *saved;
123
124 SenderState(M5Port* _port, Packet::SenderState *sender_state = NULL)
125 : port(_port), saved(sender_state)
126 {}
127 };
128
129 typedef RubyPortParams Params;
130 RubyPort(const Params *p);
131 virtual ~RubyPort() {}
132
133 void init();
134
135 MasterPort &getMasterPort(const std::string &if_name, int idx);
136 SlavePort &getSlavePort(const std::string &if_name, int idx);
137
138 virtual RequestStatus makeRequest(PacketPtr pkt) = 0;
139 virtual int outstandingCount() const = 0;
140 virtual bool isDeadlockEventScheduled() const = 0;
141 virtual void descheduleDeadlockEvent() = 0;
142
143 //
144 // Called by the controller to give the sequencer a pointer.
145 // A pointer to the controller is needed for atomic support.
146 //
147 void setController(AbstractController* _cntrl) { m_controller = _cntrl; }
148 int getId() { return m_version; }
149 unsigned int drain(Event *de);
150
151 protected:
152 const std::string m_name;
153 void ruby_hit_callback(PacketPtr pkt);
154 void testDrainComplete();
155 void ruby_eviction_callback(const Address& address);
156
157 int m_version;
158 AbstractController* m_controller;
159 MessageBuffer* m_mandatory_q_ptr;
160 PioPort pio_port;
161 bool m_usingRubyTester;
162
163 private:
164 void addToRetryList(M5Port * port)
165 {
166 if (!port->onRetryList()) {
167 port->onRetryList(true);
168 retryList.push_back(port);
169 waitingOnSequencer = true;
170 }
171 }
172
173 unsigned int getDrainCount(Event *de);
174
175 uint16_t m_port_id;
176 uint64_t m_request_cnt;
177
178 /** Vector of M5 Ports attached to this Ruby port. */
179 typedef std::vector<M5Port*>::iterator CpuPortIter;
180 std::vector<M5Port*> slave_ports;
181 std::vector<PioPort*> master_ports;
182
183 Event *drainEvent;
184
185 RubySystem* ruby_system;
186 System* system;
187
188 //
189 // Based on similar code in the M5 bus. Stores pointers to those ports
190 // that should be called when the Sequencer becomes available after a stall.
191 //
192 std::list<M5Port*> retryList;
193
194 bool waitingOnSequencer;
195 bool access_phys_mem;
196};
197
198#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 Advanced Micro Devices, Inc.
15 * Copyright (c) 2011 Mark D. Hill and David A. Wood
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
42#ifndef __MEM_RUBY_SYSTEM_RUBYPORT_HH__
43#define __MEM_RUBY_SYSTEM_RUBYPORT_HH__
44
45#include <cassert>
46#include <string>
47
48#include "mem/protocol/RequestStatus.hh"
49#include "mem/ruby/system/System.hh"
50#include "mem/mem_object.hh"
51#include "mem/physical.hh"
52#include "mem/tport.hh"
53#include "params/RubyPort.hh"
54
55class MessageBuffer;
56class AbstractController;
57
58class RubyPort : public MemObject
59{
60 public:
61 class M5Port : public QueuedSlavePort
62 {
63 private:
64
65 PacketQueue queue;
66 RubyPort *ruby_port;
67 RubySystem* ruby_system;
68 bool _onRetryList;
69 bool access_phys_mem;
70
71 public:
72 M5Port(const std::string &_name, RubyPort *_port,
73 RubySystem*_system, bool _access_phys_mem);
74 bool sendNextCycle(PacketPtr pkt);
75 void hitCallback(PacketPtr pkt);
76 void evictionCallback(const Address& address);
77 unsigned deviceBlockSize() const;
78
79 bool onRetryList()
80 { return _onRetryList; }
81
82 void onRetryList(bool newVal)
83 { _onRetryList = newVal; }
84
85 protected:
86 virtual bool recvTiming(PacketPtr pkt);
87 virtual Tick recvAtomic(PacketPtr pkt);
88 virtual void recvFunctional(PacketPtr pkt);
89 virtual AddrRangeList getAddrRanges();
90
91 private:
92 bool isPhysMemAddress(Addr addr);
93 bool doFunctionalRead(PacketPtr pkt);
94 bool doFunctionalWrite(PacketPtr pkt);
95 };
96
97 friend class M5Port;
98
99 class PioPort : public QueuedMasterPort
100 {
101 private:
102
103 PacketQueue queue;
104
105 RubyPort *ruby_port;
106
107 public:
108 PioPort(const std::string &_name, RubyPort *_port);
109 bool sendNextCycle(PacketPtr pkt);
110
111 protected:
112 virtual bool recvTiming(PacketPtr pkt);
113 virtual Tick recvAtomic(PacketPtr pkt);
114 virtual void recvFunctional(PacketPtr pkt) { }
115 };
116
117 friend class PioPort;
118
119 struct SenderState : public Packet::SenderState
120 {
121 M5Port* port;
122 Packet::SenderState *saved;
123
124 SenderState(M5Port* _port, Packet::SenderState *sender_state = NULL)
125 : port(_port), saved(sender_state)
126 {}
127 };
128
129 typedef RubyPortParams Params;
130 RubyPort(const Params *p);
131 virtual ~RubyPort() {}
132
133 void init();
134
135 MasterPort &getMasterPort(const std::string &if_name, int idx);
136 SlavePort &getSlavePort(const std::string &if_name, int idx);
137
138 virtual RequestStatus makeRequest(PacketPtr pkt) = 0;
139 virtual int outstandingCount() const = 0;
140 virtual bool isDeadlockEventScheduled() const = 0;
141 virtual void descheduleDeadlockEvent() = 0;
142
143 //
144 // Called by the controller to give the sequencer a pointer.
145 // A pointer to the controller is needed for atomic support.
146 //
147 void setController(AbstractController* _cntrl) { m_controller = _cntrl; }
148 int getId() { return m_version; }
149 unsigned int drain(Event *de);
150
151 protected:
152 const std::string m_name;
153 void ruby_hit_callback(PacketPtr pkt);
154 void testDrainComplete();
155 void ruby_eviction_callback(const Address& address);
156
157 int m_version;
158 AbstractController* m_controller;
159 MessageBuffer* m_mandatory_q_ptr;
160 PioPort pio_port;
161 bool m_usingRubyTester;
162
163 private:
164 void addToRetryList(M5Port * port)
165 {
166 if (!port->onRetryList()) {
167 port->onRetryList(true);
168 retryList.push_back(port);
169 waitingOnSequencer = true;
170 }
171 }
172
173 unsigned int getDrainCount(Event *de);
174
175 uint16_t m_port_id;
176 uint64_t m_request_cnt;
177
178 /** Vector of M5 Ports attached to this Ruby port. */
179 typedef std::vector<M5Port*>::iterator CpuPortIter;
180 std::vector<M5Port*> slave_ports;
181 std::vector<PioPort*> master_ports;
182
183 Event *drainEvent;
184
185 RubySystem* ruby_system;
186 System* system;
187
188 //
189 // Based on similar code in the M5 bus. Stores pointers to those ports
190 // that should be called when the Sequencer becomes available after a stall.
191 //
192 std::list<M5Port*> retryList;
193
194 bool waitingOnSequencer;
195 bool access_phys_mem;
196};
197
198#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__