1/*
2 * Copyright (c) 2009 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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45
46class RubyPort : public MemObject
47{
48 public:
49 class M5Port : public SimpleTimingPort
50 {
51 private:
52 RubyPort *ruby_port;
53 bool _onRetryList;
54 bool access_phys_mem;
55
56 public:
57 M5Port(const std::string &_name, RubyPort *_port,
58 bool _access_phys_mem);
59 bool sendTiming(PacketPtr pkt);
60 void hitCallback(PacketPtr pkt);
61 unsigned deviceBlockSize() const;
62
63 bool onRetryList()
64 { return _onRetryList; }
65
66 void onRetryList(bool newVal)
67 { _onRetryList = newVal; }
68
69 protected:
70 virtual bool recvTiming(PacketPtr pkt);
71 virtual Tick recvAtomic(PacketPtr pkt);
72
73 private:
74 bool isPhysMemAddress(Addr addr);
75 };
76
77 friend class M5Port;
78
79 class PioPort : public SimpleTimingPort
80 {
81 private:
82 RubyPort *ruby_port;

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140 }
141
142 uint16_t m_port_id;
143 uint64_t m_request_cnt;
144
145 M5Port* physMemPort;
146
147 PhysicalMemory* physmem;
148
149 //
150 // Based on similar code in the M5 bus. Stores pointers to those ports
151 // that should be called when the Sequencer becomes available after a stall.
152 //
153 std::list<M5Port*> retryList;
154
155 bool waitingOnSequencer;
156 bool access_phys_mem;
157};
158
159#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__