1/*
2 * Copyright (c) 2009 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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45
46class RubyPort : public MemObject
47{
48 public:
49 class M5Port : public SimpleTimingPort
50 {
51 private:
52 RubyPort *ruby_port;
53 RubySystem* ruby_system;
54 bool _onRetryList;
55 bool access_phys_mem;
56
57 public:
58 M5Port(const std::string &_name, RubyPort *_port,
59 RubySystem*_system, bool _access_phys_mem);
60 bool sendTiming(PacketPtr pkt);
61 void hitCallback(PacketPtr pkt);
62 unsigned deviceBlockSize() const;
63
64 bool onRetryList()
65 { return _onRetryList; }
66
67 void onRetryList(bool newVal)
68 { _onRetryList = newVal; }
69
70 protected:
71 virtual bool recvTiming(PacketPtr pkt);
72 virtual Tick recvAtomic(PacketPtr pkt);
73 virtual void recvFunctional(PacketPtr pkt);
74
75 private:
76 bool isPhysMemAddress(Addr addr);
77 bool doFunctionalRead(PacketPtr pkt);
78 bool doFunctionalWrite(PacketPtr pkt);
79 };
80
81 friend class M5Port;
82
83 class PioPort : public SimpleTimingPort
84 {
85 private:
86 RubyPort *ruby_port;

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144 }
145
146 uint16_t m_port_id;
147 uint64_t m_request_cnt;
148
149 M5Port* physMemPort;
150
151 PhysicalMemory* physmem;
152 RubySystem* ruby_system;
153
154 //
155 // Based on similar code in the M5 bus. Stores pointers to those ports
156 // that should be called when the Sequencer becomes available after a stall.
157 //
158 std::list<M5Port*> retryList;
159
160 bool waitingOnSequencer;
161 bool access_phys_mem;
162};
163
164#endif // __MEM_RUBY_SYSTEM_RUBYPORT_HH__