RubyPort.cc (9542:683991c46ac8) RubyPort.cc (9557:8666e81607a6)
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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114 }
115
116 return *slave_ports[idx];
117 }
118}
119
120RubyPort::PioPort::PioPort(const std::string &_name,
121 RubyPort *_port)
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 105 unchanged lines hidden (view full) ---

114 }
115
116 return *slave_ports[idx];
117 }
118}
119
120RubyPort::PioPort::PioPort(const std::string &_name,
121 RubyPort *_port)
122 : QueuedMasterPort(_name, _port, queue), queue(*_port, *this),
123 ruby_port(_port)
122 : QueuedMasterPort(_name, _port, queue), queue(*_port, *this)
124{
125 DPRINTF(RubyPort, "creating master port on ruby sequencer %s\n", _name);
126}
127
128RubyPort::M5Port::M5Port(const std::string &_name, RubyPort *_port,
129 RubySystem *_system, bool _access_phys_mem)
130 : QueuedSlavePort(_name, _port, queue), queue(*_port, *this),
131 ruby_port(_port), ruby_system(_system),

--- 379 unchanged lines hidden --- 		123{
124 DPRINTF(RubyPort, "creating master port on ruby sequencer %s\n", _name);
125}
126
127RubyPort::M5Port::M5Port(const std::string &_name, RubyPort *_port,
128 RubySystem *_system, bool _access_phys_mem)
129 : QueuedSlavePort(_name, _port, queue), queue(*_port, *this),
130 ruby_port(_port), ruby_system(_system),

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