RubyPort.cc (9270:92aad0e984ff) | RubyPort.cc (9294:8fb03b13de02) |
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1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 64 unchanged lines hidden (view full) --- 73 74void 75RubyPort::init() 76{ 77 assert(m_controller != NULL); 78 m_mandatory_q_ptr = m_controller->getMandatoryQueue(); 79} 80 | 1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 64 unchanged lines hidden (view full) --- 73 74void 75RubyPort::init() 76{ 77 assert(m_controller != NULL); 78 m_mandatory_q_ptr = m_controller->getMandatoryQueue(); 79} 80 |
81MasterPort & 82RubyPort::getMasterPort(const std::string &if_name, int idx) | 81BaseMasterPort & 82RubyPort::getMasterPort(const std::string &if_name, PortID idx) |
83{ 84 if (if_name == "pio_port") { 85 return pio_port; 86 } 87 88 // used by the x86 CPUs to connect the interrupt PIO and interrupt slave 89 // port 90 if (if_name != "master") { 91 // pass it along to our super class 92 return MemObject::getMasterPort(if_name, idx); 93 } else { | 83{ 84 if (if_name == "pio_port") { 85 return pio_port; 86 } 87 88 // used by the x86 CPUs to connect the interrupt PIO and interrupt slave 89 // port 90 if (if_name != "master") { 91 // pass it along to our super class 92 return MemObject::getMasterPort(if_name, idx); 93 } else { |
94 if (idx >= static_cast<int>(master_ports.size())) { | 94 if (idx >= static_cast<PortID>(master_ports.size())) { |
95 panic("RubyPort::getMasterPort: unknown index %d\n", idx); 96 } 97 98 return *master_ports[idx]; 99 } 100} 101 | 95 panic("RubyPort::getMasterPort: unknown index %d\n", idx); 96 } 97 98 return *master_ports[idx]; 99 } 100} 101 |
102SlavePort & 103RubyPort::getSlavePort(const std::string &if_name, int idx) | 102BaseSlavePort & 103RubyPort::getSlavePort(const std::string &if_name, PortID idx) |
104{ 105 // used by the CPUs to connect the caches to the interconnect, and 106 // for the x86 case also the interrupt master 107 if (if_name != "slave") { 108 // pass it along to our super class 109 return MemObject::getSlavePort(if_name, idx); 110 } else { | 104{ 105 // used by the CPUs to connect the caches to the interconnect, and 106 // for the x86 case also the interrupt master 107 if (if_name != "slave") { 108 // pass it along to our super class 109 return MemObject::getSlavePort(if_name, idx); 110 } else { |
111 if (idx >= static_cast<int>(slave_ports.size())) { | 111 if (idx >= static_cast<PortID>(slave_ports.size())) { |
112 panic("RubyPort::getSlavePort: unknown index %d\n", idx); 113 } 114 115 return *slave_ports[idx]; 116 } 117} 118 119RubyPort::PioPort::PioPort(const std::string &_name, --- 393 unchanged lines hidden --- | 112 panic("RubyPort::getSlavePort: unknown index %d\n", idx); 113 } 114 115 return *slave_ports[idx]; 116 } 117} 118 119RubyPort::PioPort::PioPort(const std::string &_name, --- 393 unchanged lines hidden --- |