RubyPort.cc (9206:f6483789d23a) RubyPort.cc (9208:2451e60d4555)
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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270 // or not.
271 num_backing_store++;
272 else if (access_perm == AccessPermission_Invalid ||
273 access_perm == AccessPermission_NotPresent)
274 num_invalid++;
275 }
276 assert(num_rw <= 1);
277
1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 261 unchanged lines hidden (view full) ---

270 // or not.
271 num_backing_store++;
272 else if (access_perm == AccessPermission_Invalid ||
273 access_perm == AccessPermission_NotPresent)
274 num_invalid++;
275 }
276 assert(num_rw <= 1);
277
278 uint8* data = pkt->getPtr<uint8_t>(true);
278 uint8_t *data = pkt->getPtr<uint8_t>(true);
279 unsigned int size_in_bytes = pkt->getSize();
280 unsigned startByte = address.getAddress() - line_address.getAddress();
281
282 // This if case is meant to capture what happens in a Broadcast/Snoop
283 // protocol where the block does not exist in the cache hierarchy. You
284 // only want to read from the Backing_Store memory if there is no copy in
285 // the cache hierarchy, otherwise you want to try to read the RO or RW
286 // copies existing in the cache hierarchy (covered by the else statement).

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382 // also we let the access go through. Or, if there is no copy in the cache
383 // hierarchy at all, we still want to do the write to the memory
384 // (Backing_Store) instead of failing.
385
386 DPRINTF(RubyPort, "num_busy = %d, num_ro = %d, num_rw = %d\n",
387 num_busy, num_ro, num_rw);
388 assert(num_rw <= 1);
389
279 unsigned int size_in_bytes = pkt->getSize();
280 unsigned startByte = address.getAddress() - line_address.getAddress();
281
282 // This if case is meant to capture what happens in a Broadcast/Snoop
283 // protocol where the block does not exist in the cache hierarchy. You
284 // only want to read from the Backing_Store memory if there is no copy in
285 // the cache hierarchy, otherwise you want to try to read the RO or RW
286 // copies existing in the cache hierarchy (covered by the else statement).

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382 // also we let the access go through. Or, if there is no copy in the cache
383 // hierarchy at all, we still want to do the write to the memory
384 // (Backing_Store) instead of failing.
385
386 DPRINTF(RubyPort, "num_busy = %d, num_ro = %d, num_rw = %d\n",
387 num_busy, num_ro, num_rw);
388 assert(num_rw <= 1);
389
390 uint8* data = pkt->getPtr<uint8_t>(true);
390 uint8_t *data = pkt->getPtr<uint8_t>(true);
391 unsigned int size_in_bytes = pkt->getSize();
392 unsigned startByte = addr.getAddress() - line_addr.getAddress();
393
394 if ((num_busy == 0 && num_ro > 0) || num_rw == 1 ||
395 (num_invalid == (num_controllers - 1) && num_backing_store == 1))
396 {
397 for(int i = 0; i < num_controllers;++i) {
398 access_perm = ruby_system->m_abs_cntrl_vec[i]->

--- 297 unchanged lines hidden --- 		391 unsigned int size_in_bytes = pkt->getSize();
392 unsigned startByte = addr.getAddress() - line_addr.getAddress();
393
394 if ((num_busy == 0 && num_ro > 0) || num_rw == 1 ||
395 (num_invalid == (num_controllers - 1) && num_backing_store == 1))
396 {
397 for(int i = 0; i < num_controllers;++i) {
398 access_perm = ruby_system->m_abs_cntrl_vec[i]->

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