RubyPort.cc (8874:9e2a4cf89be6) RubyPort.cc (8914:8c3bd7bea667)
1/*
2 * Copyright (c) 2009 Advanced Micro Devices, Inc.
3 * Copyright (c) 2011 Mark D. Hill and David A. Wood
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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93 return &physMemPort;
94 }
95
96 return NULL;
97}
98
99RubyPort::PioPort::PioPort(const std::string &_name,
100 RubyPort *_port)
1/*
2 * Copyright (c) 2009 Advanced Micro Devices, Inc.
3 * Copyright (c) 2011 Mark D. Hill and David A. Wood
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions are
8 * met: redistributions of source code must retain the above copyright

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93 return &physMemPort;
94 }
95
96 return NULL;
97}
98
99RubyPort::PioPort::PioPort(const std::string &_name,
100 RubyPort *_port)
101 : SimpleTimingPort(_name, _port)
101 : QueuedPort(_name, _port, queue), queue(*_port, *this), ruby_port(_port)
102{
103 DPRINTF(RubyPort, "creating port to ruby sequencer to cpu %s\n", _name);
102{
103 DPRINTF(RubyPort, "creating port to ruby sequencer to cpu %s\n", _name);
104 ruby_port = _port;
105}
106
107RubyPort::M5Port::M5Port(const std::string &_name, RubyPort *_port,
108 RubySystem *_system, bool _access_phys_mem)
104}
105
106RubyPort::M5Port::M5Port(const std::string &_name, RubyPort *_port,
107 RubySystem *_system, bool _access_phys_mem)
109 : SimpleTimingPort(_name, _port)
108 : QueuedPort(_name, _port, queue), queue(*_port, *this),
109 ruby_port(_port), ruby_system(_system),
110 _onRetryList(false), access_phys_mem(_access_phys_mem)
110{
111 DPRINTF(RubyPort, "creating port from ruby sequcner to cpu %s\n", _name);
111{
112 DPRINTF(RubyPort, "creating port from ruby sequcner to cpu %s\n", _name);
112 ruby_port = _port;
113 ruby_system = _system;
114 _onRetryList = false;
115 access_phys_mem = _access_phys_mem;
116}
117
118Tick
119RubyPort::PioPort::recvAtomic(PacketPtr pkt)
120{
121 panic("RubyPort::PioPort::recvAtomic() not implemented!\n");
122 return 0;
123}

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643 }
644 DPRINTF(RubyPort, "Hit callback done!\n");
645}
646
647bool
648RubyPort::M5Port::sendNextCycle(PacketPtr pkt)
649{
650 //minimum latency, must be > 0
113}
114
115Tick
116RubyPort::PioPort::recvAtomic(PacketPtr pkt)
117{
118 panic("RubyPort::PioPort::recvAtomic() not implemented!\n");
119 return 0;
120}

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640 }
641 DPRINTF(RubyPort, "Hit callback done!\n");
642}
643
644bool
645RubyPort::M5Port::sendNextCycle(PacketPtr pkt)
646{
647 //minimum latency, must be > 0
651 schedSendTiming(pkt, curTick() + (1 * g_eventQueue_ptr->getClock()));
648 queue.schedSendTiming(pkt, curTick() + (1 * g_eventQueue_ptr->getClock()));
652 return true;
653}
654
655bool
656RubyPort::PioPort::sendNextCycle(PacketPtr pkt)
657{
658 //minimum latency, must be > 0
649 return true;
650}
651
652bool
653RubyPort::PioPort::sendNextCycle(PacketPtr pkt)
654{
655 //minimum latency, must be > 0
659 schedSendTiming(pkt, curTick() + (1 * g_eventQueue_ptr->getClock()));
656 queue.schedSendTiming(pkt, curTick() + (1 * g_eventQueue_ptr->getClock()));
660 return true;
661}
662
663bool
664RubyPort::M5Port::isPhysMemAddress(Addr addr)
665{
666 AddrRangeList physMemAddrList =
667 ruby_port->physMemPort.getPeer()->getAddrRanges();

--- 28 unchanged lines hidden --- 		657 return true;
658}
659
660bool
661RubyPort::M5Port::isPhysMemAddress(Addr addr)
662{
663 AddrRangeList physMemAddrList =
664 ruby_port->physMemPort.getPeer()->getAddrRanges();

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