1/* 2 * Copyright (c) 2012-2013 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 217 unchanged lines hidden (view full) --- 226 227bool 228RubyPort::MemSlavePort::recvTimingReq(PacketPtr pkt) 229{ 230 DPRINTF(RubyPort, "Timing request for address %#x on port %d\n", 231 pkt->getAddr(), id); 232 RubyPort *ruby_port = static_cast<RubyPort *>(&owner); 233 |
234 if (pkt->cacheResponding()) 235 panic("RubyPort should never see request with the " 236 "cacheResponding flag set\n"); |
237 238 // Check for pio requests and directly send them to the dedicated 239 // pio port. 240 if (!isPhysMemAddress(pkt->getAddr())) { 241 assert(ruby_port->memMasterPort.isConnected()); 242 DPRINTF(RubyPort, "Request address %#x assumed to be a pio address\n", 243 pkt->getAddr()); 244 --- 306 unchanged lines hidden --- |