1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 Advanced Micro Devices, Inc.
15 * Copyright (c) 2011 Mark D. Hill and David A. Wood
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
42#include "cpu/testers/rubytest/RubyTester.hh"
43#include "debug/Config.hh"
44#include "debug/Drain.hh"
45#include "debug/Ruby.hh"
46#include "mem/protocol/AccessPermission.hh"
47#include "mem/ruby/slicc_interface/AbstractController.hh"
48#include "mem/ruby/system/RubyPort.hh"
49#include "sim/system.hh"
50
51RubyPort::RubyPort(const Params *p)
52 : MemObject(p), m_version(p->version), m_controller(NULL),
53 m_mandatory_q_ptr(NULL),
54 pio_port(csprintf("%s-pio-port", name()), this),
55 m_usingRubyTester(p->using_ruby_tester), m_request_cnt(0),
56 drainManager(NULL), ruby_system(p->ruby_system), system(p->system),
57 waitingOnSequencer(false), access_phys_mem(p->access_phys_mem)
58{
59 assert(m_version != -1);
60
61 // create the slave ports based on the number of connected ports
62 for (size_t i = 0; i < p->port_slave_connection_count; ++i) {
63 slave_ports.push_back(new M5Port(csprintf("%s-slave%d", name(), i),
64 this, ruby_system, access_phys_mem));
65 }
66
67 // create the master ports based on the number of connected ports
68 for (size_t i = 0; i < p->port_master_connection_count; ++i) {
69 master_ports.push_back(new PioPort(csprintf("%s-master%d", name(), i),
70 this));
71 }
72}
73
74void
75RubyPort::init()
76{
77 assert(m_controller != NULL);
78 m_mandatory_q_ptr = m_controller->getMandatoryQueue();
79 m_mandatory_q_ptr->setSender(this);
80}
81
82BaseMasterPort &
83RubyPort::getMasterPort(const std::string &if_name, PortID idx)
84{
85 if (if_name == "pio_port") {
86 return pio_port;
87 }
88
89 // used by the x86 CPUs to connect the interrupt PIO and interrupt slave
90 // port
91 if (if_name != "master") {
92 // pass it along to our super class
93 return MemObject::getMasterPort(if_name, idx);
94 } else {
95 if (idx >= static_cast<PortID>(master_ports.size())) {
96 panic("RubyPort::getMasterPort: unknown index %d\n", idx);
97 }
98
99 return *master_ports[idx];
100 }
101}
102
103BaseSlavePort &
104RubyPort::getSlavePort(const std::string &if_name, PortID idx)
105{
106 // used by the CPUs to connect the caches to the interconnect, and
107 // for the x86 case also the interrupt master
108 if (if_name != "slave") {
109 // pass it along to our super class
110 return MemObject::getSlavePort(if_name, idx);
111 } else {
112 if (idx >= static_cast<PortID>(slave_ports.size())) {
113 panic("RubyPort::getSlavePort: unknown index %d\n", idx);
114 }
115
116 return *slave_ports[idx];
117 }
118}
119
120RubyPort::PioPort::PioPort(const std::string &_name,
121 RubyPort *_port)
122 : QueuedMasterPort(_name, _port, queue), queue(*_port, *this),
123 ruby_port(_port)
124{
125 DPRINTF(RubyPort, "creating master port on ruby sequencer %s\n", _name);
126}
127
128RubyPort::M5Port::M5Port(const std::string &_name, RubyPort *_port,
129 RubySystem *_system, bool _access_phys_mem)
130 : QueuedSlavePort(_name, _port, queue), queue(*_port, *this),
131 ruby_port(_port), ruby_system(_system),
132 _onRetryList(false), access_phys_mem(_access_phys_mem)
133{
134 DPRINTF(RubyPort, "creating slave port on ruby sequencer %s\n", _name);
135}
136
137Tick
138RubyPort::M5Port::recvAtomic(PacketPtr pkt)
139{
140 panic("RubyPort::M5Port::recvAtomic() not implemented!\n");
141 return 0;
142}
143
144
145bool
146RubyPort::PioPort::recvTimingResp(PacketPtr pkt)
147{
148 // In FS mode, ruby memory will receive pio responses from devices
149 // and it must forward these responses back to the particular CPU.
150 DPRINTF(RubyPort, "Pio response for address %#x\n", pkt->getAddr());
151
152 // First we must retrieve the request port from the sender State
153 RubyPort::SenderState *senderState =
| 1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 Advanced Micro Devices, Inc.
15 * Copyright (c) 2011 Mark D. Hill and David A. Wood
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
42#include "cpu/testers/rubytest/RubyTester.hh"
43#include "debug/Config.hh"
44#include "debug/Drain.hh"
45#include "debug/Ruby.hh"
46#include "mem/protocol/AccessPermission.hh"
47#include "mem/ruby/slicc_interface/AbstractController.hh"
48#include "mem/ruby/system/RubyPort.hh"
49#include "sim/system.hh"
50
51RubyPort::RubyPort(const Params *p)
52 : MemObject(p), m_version(p->version), m_controller(NULL),
53 m_mandatory_q_ptr(NULL),
54 pio_port(csprintf("%s-pio-port", name()), this),
55 m_usingRubyTester(p->using_ruby_tester), m_request_cnt(0),
56 drainManager(NULL), ruby_system(p->ruby_system), system(p->system),
57 waitingOnSequencer(false), access_phys_mem(p->access_phys_mem)
58{
59 assert(m_version != -1);
60
61 // create the slave ports based on the number of connected ports
62 for (size_t i = 0; i < p->port_slave_connection_count; ++i) {
63 slave_ports.push_back(new M5Port(csprintf("%s-slave%d", name(), i),
64 this, ruby_system, access_phys_mem));
65 }
66
67 // create the master ports based on the number of connected ports
68 for (size_t i = 0; i < p->port_master_connection_count; ++i) {
69 master_ports.push_back(new PioPort(csprintf("%s-master%d", name(), i),
70 this));
71 }
72}
73
74void
75RubyPort::init()
76{
77 assert(m_controller != NULL);
78 m_mandatory_q_ptr = m_controller->getMandatoryQueue();
79 m_mandatory_q_ptr->setSender(this);
80}
81
82BaseMasterPort &
83RubyPort::getMasterPort(const std::string &if_name, PortID idx)
84{
85 if (if_name == "pio_port") {
86 return pio_port;
87 }
88
89 // used by the x86 CPUs to connect the interrupt PIO and interrupt slave
90 // port
91 if (if_name != "master") {
92 // pass it along to our super class
93 return MemObject::getMasterPort(if_name, idx);
94 } else {
95 if (idx >= static_cast<PortID>(master_ports.size())) {
96 panic("RubyPort::getMasterPort: unknown index %d\n", idx);
97 }
98
99 return *master_ports[idx];
100 }
101}
102
103BaseSlavePort &
104RubyPort::getSlavePort(const std::string &if_name, PortID idx)
105{
106 // used by the CPUs to connect the caches to the interconnect, and
107 // for the x86 case also the interrupt master
108 if (if_name != "slave") {
109 // pass it along to our super class
110 return MemObject::getSlavePort(if_name, idx);
111 } else {
112 if (idx >= static_cast<PortID>(slave_ports.size())) {
113 panic("RubyPort::getSlavePort: unknown index %d\n", idx);
114 }
115
116 return *slave_ports[idx];
117 }
118}
119
120RubyPort::PioPort::PioPort(const std::string &_name,
121 RubyPort *_port)
122 : QueuedMasterPort(_name, _port, queue), queue(*_port, *this),
123 ruby_port(_port)
124{
125 DPRINTF(RubyPort, "creating master port on ruby sequencer %s\n", _name);
126}
127
128RubyPort::M5Port::M5Port(const std::string &_name, RubyPort *_port,
129 RubySystem *_system, bool _access_phys_mem)
130 : QueuedSlavePort(_name, _port, queue), queue(*_port, *this),
131 ruby_port(_port), ruby_system(_system),
132 _onRetryList(false), access_phys_mem(_access_phys_mem)
133{
134 DPRINTF(RubyPort, "creating slave port on ruby sequencer %s\n", _name);
135}
136
137Tick
138RubyPort::M5Port::recvAtomic(PacketPtr pkt)
139{
140 panic("RubyPort::M5Port::recvAtomic() not implemented!\n");
141 return 0;
142}
143
144
145bool
146RubyPort::PioPort::recvTimingResp(PacketPtr pkt)
147{
148 // In FS mode, ruby memory will receive pio responses from devices
149 // and it must forward these responses back to the particular CPU.
150 DPRINTF(RubyPort, "Pio response for address %#x\n", pkt->getAddr());
151
152 // First we must retrieve the request port from the sender State
153 RubyPort::SenderState *senderState =
|
154 safe_cast<RubyPort::SenderState *>(pkt->senderState);
| 154 safe_cast<RubyPort::SenderState *>(pkt->popSenderState());
|
155 M5Port *port = senderState->port;
156 assert(port != NULL);
| 155 M5Port *port = senderState->port;
156 assert(port != NULL);
|
157
158 // pop the sender state from the packet
159 pkt->senderState = senderState->saved;
| |
160 delete senderState;
161
162 port->sendTimingResp(pkt);
163
164 return true;
165}
166
167bool
168RubyPort::M5Port::recvTimingReq(PacketPtr pkt)
169{
170 DPRINTF(RubyPort,
171 "Timing access caught for address %#x\n", pkt->getAddr());
172
173 //dsm: based on SimpleTimingPort::recvTimingReq(pkt);
174
175 // The received packets should only be M5 requests, which should never
176 // get nacked. There used to be code to hanldle nacks here, but
177 // I'm pretty sure it didn't work correctly with the drain code,
178 // so that would need to be fixed if we ever added it back.
179
180 if (pkt->memInhibitAsserted()) {
181 warn("memInhibitAsserted???");
182 // snooper will supply based on copy of packet
183 // still target's responsibility to delete packet
184 delete pkt;
185 return true;
186 }
187
188 // Save the port in the sender state object to be used later to
189 // route the response
| 157 delete senderState;
158
159 port->sendTimingResp(pkt);
160
161 return true;
162}
163
164bool
165RubyPort::M5Port::recvTimingReq(PacketPtr pkt)
166{
167 DPRINTF(RubyPort,
168 "Timing access caught for address %#x\n", pkt->getAddr());
169
170 //dsm: based on SimpleTimingPort::recvTimingReq(pkt);
171
172 // The received packets should only be M5 requests, which should never
173 // get nacked. There used to be code to hanldle nacks here, but
174 // I'm pretty sure it didn't work correctly with the drain code,
175 // so that would need to be fixed if we ever added it back.
176
177 if (pkt->memInhibitAsserted()) {
178 warn("memInhibitAsserted???");
179 // snooper will supply based on copy of packet
180 // still target's responsibility to delete packet
181 delete pkt;
182 return true;
183 }
184
185 // Save the port in the sender state object to be used later to
186 // route the response
|
190 pkt->senderState = new SenderState(this, pkt->senderState);
| 187 pkt->pushSenderState(new SenderState(this));
|
191
192 // Check for pio requests and directly send them to the dedicated
193 // pio port.
194 if (!isPhysMemAddress(pkt->getAddr())) {
195 assert(ruby_port->pio_port.isConnected());
196 DPRINTF(RubyPort,
197 "Request for address 0x%#x is assumed to be a pio request\n",
198 pkt->getAddr());
199
200 // send next cycle
201 ruby_port->pio_port.schedTimingReq(pkt,
202 curTick() + g_system_ptr->clockPeriod());
203 return true;
204 }
205
206 assert(Address(pkt->getAddr()).getOffset() + pkt->getSize() <=
207 RubySystem::getBlockSizeBytes());
208
209 // Submit the ruby request
210 RequestStatus requestStatus = ruby_port->makeRequest(pkt);
211
212 // If the request successfully issued then we should return true.
213 // Otherwise, we need to delete the senderStatus we just created and return
214 // false.
215 if (requestStatus == RequestStatus_Issued) {
216 DPRINTF(RubyPort, "Request %#x issued\n", pkt->getAddr());
217 return true;
218 }
219
220 //
221 // Unless one is using the ruby tester, record the stalled M5 port for
222 // later retry when the sequencer becomes free.
223 //
224 if (!ruby_port->m_usingRubyTester) {
225 ruby_port->addToRetryList(this);
226 }
227
228 DPRINTF(RubyPort,
229 "Request for address %#x did not issue because %s\n",
230 pkt->getAddr(), RequestStatus_to_string(requestStatus));
231
232 SenderState* senderState = safe_cast<SenderState*>(pkt->senderState);
| 188
189 // Check for pio requests and directly send them to the dedicated
190 // pio port.
191 if (!isPhysMemAddress(pkt->getAddr())) {
192 assert(ruby_port->pio_port.isConnected());
193 DPRINTF(RubyPort,
194 "Request for address 0x%#x is assumed to be a pio request\n",
195 pkt->getAddr());
196
197 // send next cycle
198 ruby_port->pio_port.schedTimingReq(pkt,
199 curTick() + g_system_ptr->clockPeriod());
200 return true;
201 }
202
203 assert(Address(pkt->getAddr()).getOffset() + pkt->getSize() <=
204 RubySystem::getBlockSizeBytes());
205
206 // Submit the ruby request
207 RequestStatus requestStatus = ruby_port->makeRequest(pkt);
208
209 // If the request successfully issued then we should return true.
210 // Otherwise, we need to delete the senderStatus we just created and return
211 // false.
212 if (requestStatus == RequestStatus_Issued) {
213 DPRINTF(RubyPort, "Request %#x issued\n", pkt->getAddr());
214 return true;
215 }
216
217 //
218 // Unless one is using the ruby tester, record the stalled M5 port for
219 // later retry when the sequencer becomes free.
220 //
221 if (!ruby_port->m_usingRubyTester) {
222 ruby_port->addToRetryList(this);
223 }
224
225 DPRINTF(RubyPort,
226 "Request for address %#x did not issue because %s\n",
227 pkt->getAddr(), RequestStatus_to_string(requestStatus));
228
229 SenderState* senderState = safe_cast<SenderState*>(pkt->senderState);
|
233 pkt->senderState = senderState->saved;
| 230 pkt->senderState = senderState->predecessor;
|
234 delete senderState;
235 return false;
236}
237
238void
239RubyPort::M5Port::recvFunctional(PacketPtr pkt)
240{
241 DPRINTF(RubyPort, "Functional access caught for address %#x\n",
242 pkt->getAddr());
243
244 // Check for pio requests and directly send them to the dedicated
245 // pio port.
246 if (!isPhysMemAddress(pkt->getAddr())) {
247 assert(ruby_port->pio_port.isConnected());
248 DPRINTF(RubyPort, "Request for address 0x%#x is a pio request\n",
249 pkt->getAddr());
250 panic("RubyPort::PioPort::recvFunctional() not implemented!\n");
251 }
252
253 assert(pkt->getAddr() + pkt->getSize() <=
254 line_address(Address(pkt->getAddr())).getAddress() +
255 RubySystem::getBlockSizeBytes());
256
257 bool accessSucceeded = false;
258 bool needsResponse = pkt->needsResponse();
259
260 // Do the functional access on ruby memory
261 if (pkt->isRead()) {
262 accessSucceeded = ruby_system->functionalRead(pkt);
263 } else if (pkt->isWrite()) {
264 accessSucceeded = ruby_system->functionalWrite(pkt);
265 } else {
266 panic("RubyPort: unsupported functional command %s\n",
267 pkt->cmdString());
268 }
269
270 // Unless the requester explicitly said otherwise, generate an error if
271 // the functional request failed
272 if (!accessSucceeded && !pkt->suppressFuncError()) {
273 fatal("Ruby functional %s failed for address %#x\n",
274 pkt->isWrite() ? "write" : "read", pkt->getAddr());
275 }
276
277 if (access_phys_mem) {
278 // The attached physmem contains the official version of data.
279 // The following command performs the real functional access.
280 // This line should be removed once Ruby supplies the official version
281 // of data.
282 ruby_port->system->getPhysMem().functionalAccess(pkt);
283 }
284
285 // turn packet around to go back to requester if response expected
286 if (needsResponse) {
287 pkt->setFunctionalResponseStatus(accessSucceeded);
288
289 // @todo There should not be a reverse call since the response is
290 // communicated through the packet pointer
291 // DPRINTF(RubyPort, "Sending packet back over port\n");
292 // sendFunctional(pkt);
293 }
294 DPRINTF(RubyPort, "Functional access %s!\n",
295 accessSucceeded ? "successful":"failed");
296}
297
298void
299RubyPort::ruby_hit_callback(PacketPtr pkt)
300{
301 // Retrieve the request port from the sender State
302 RubyPort::SenderState *senderState =
303 safe_cast<RubyPort::SenderState *>(pkt->senderState);
304 M5Port *port = senderState->port;
305 assert(port != NULL);
306
307 // pop the sender state from the packet
| 231 delete senderState;
232 return false;
233}
234
235void
236RubyPort::M5Port::recvFunctional(PacketPtr pkt)
237{
238 DPRINTF(RubyPort, "Functional access caught for address %#x\n",
239 pkt->getAddr());
240
241 // Check for pio requests and directly send them to the dedicated
242 // pio port.
243 if (!isPhysMemAddress(pkt->getAddr())) {
244 assert(ruby_port->pio_port.isConnected());
245 DPRINTF(RubyPort, "Request for address 0x%#x is a pio request\n",
246 pkt->getAddr());
247 panic("RubyPort::PioPort::recvFunctional() not implemented!\n");
248 }
249
250 assert(pkt->getAddr() + pkt->getSize() <=
251 line_address(Address(pkt->getAddr())).getAddress() +
252 RubySystem::getBlockSizeBytes());
253
254 bool accessSucceeded = false;
255 bool needsResponse = pkt->needsResponse();
256
257 // Do the functional access on ruby memory
258 if (pkt->isRead()) {
259 accessSucceeded = ruby_system->functionalRead(pkt);
260 } else if (pkt->isWrite()) {
261 accessSucceeded = ruby_system->functionalWrite(pkt);
262 } else {
263 panic("RubyPort: unsupported functional command %s\n",
264 pkt->cmdString());
265 }
266
267 // Unless the requester explicitly said otherwise, generate an error if
268 // the functional request failed
269 if (!accessSucceeded && !pkt->suppressFuncError()) {
270 fatal("Ruby functional %s failed for address %#x\n",
271 pkt->isWrite() ? "write" : "read", pkt->getAddr());
272 }
273
274 if (access_phys_mem) {
275 // The attached physmem contains the official version of data.
276 // The following command performs the real functional access.
277 // This line should be removed once Ruby supplies the official version
278 // of data.
279 ruby_port->system->getPhysMem().functionalAccess(pkt);
280 }
281
282 // turn packet around to go back to requester if response expected
283 if (needsResponse) {
284 pkt->setFunctionalResponseStatus(accessSucceeded);
285
286 // @todo There should not be a reverse call since the response is
287 // communicated through the packet pointer
288 // DPRINTF(RubyPort, "Sending packet back over port\n");
289 // sendFunctional(pkt);
290 }
291 DPRINTF(RubyPort, "Functional access %s!\n",
292 accessSucceeded ? "successful":"failed");
293}
294
295void
296RubyPort::ruby_hit_callback(PacketPtr pkt)
297{
298 // Retrieve the request port from the sender State
299 RubyPort::SenderState *senderState =
300 safe_cast<RubyPort::SenderState *>(pkt->senderState);
301 M5Port *port = senderState->port;
302 assert(port != NULL);
303
304 // pop the sender state from the packet
|
308 pkt->senderState = senderState->saved;
| 305 pkt->senderState = senderState->predecessor;
|
309 delete senderState;
310
311 port->hitCallback(pkt);
312
313 //
314 // If we had to stall the M5Ports, wake them up because the sequencer
315 // likely has free resources now.
316 //
317 if (waitingOnSequencer) {
318 //
319 // Record the current list of ports to retry on a temporary list before
320 // calling sendRetry on those ports. sendRetry will cause an
321 // immediate retry, which may result in the ports being put back on the
322 // list. Therefore we want to clear the retryList before calling
323 // sendRetry.
324 //
325 std::list<M5Port*> curRetryList(retryList);
326
327 retryList.clear();
328 waitingOnSequencer = false;
329
330 for (std::list<M5Port*>::iterator i = curRetryList.begin();
331 i != curRetryList.end(); ++i) {
332 DPRINTF(RubyPort,
333 "Sequencer may now be free. SendRetry to port %s\n",
334 (*i)->name());
335 (*i)->onRetryList(false);
336 (*i)->sendRetry();
337 }
338 }
339
340 testDrainComplete();
341}
342
343void
344RubyPort::testDrainComplete()
345{
346 //If we weren't able to drain before, we might be able to now.
347 if (drainManager != NULL) {
348 unsigned int drainCount = outstandingCount();
349 DPRINTF(Drain, "Drain count: %u\n", drainCount);
350 if (drainCount == 0) {
351 DPRINTF(Drain, "RubyPort done draining, signaling drain done\n");
352 drainManager->signalDrainDone();
353 // Clear the drain manager once we're done with it.
354 drainManager = NULL;
355 }
356 }
357}
358
359unsigned int
360RubyPort::getChildDrainCount(DrainManager *dm)
361{
362 int count = 0;
363
364 if (pio_port.isConnected()) {
365 count += pio_port.drain(dm);
366 DPRINTF(Config, "count after pio check %d\n", count);
367 }
368
369 for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) {
370 count += (*p)->drain(dm);
371 DPRINTF(Config, "count after slave port check %d\n", count);
372 }
373
374 for (std::vector<PioPort*>::iterator p = master_ports.begin();
375 p != master_ports.end(); ++p) {
376 count += (*p)->drain(dm);
377 DPRINTF(Config, "count after master port check %d\n", count);
378 }
379
380 DPRINTF(Config, "final count %d\n", count);
381
382 return count;
383}
384
385unsigned int
386RubyPort::drain(DrainManager *dm)
387{
388 if (isDeadlockEventScheduled()) {
389 descheduleDeadlockEvent();
390 }
391
392 //
393 // If the RubyPort is not empty, then it needs to clear all outstanding
394 // requests before it should call drainManager->signalDrainDone()
395 //
396 DPRINTF(Config, "outstanding count %d\n", outstandingCount());
397 bool need_drain = outstandingCount() > 0;
398
399 //
400 // Also, get the number of child ports that will also need to clear
401 // their buffered requests before they call drainManager->signalDrainDone()
402 //
403 unsigned int child_drain_count = getChildDrainCount(dm);
404
405 // Set status
406 if (need_drain) {
407 drainManager = dm;
408
409 DPRINTF(Drain, "RubyPort not drained\n");
410 setDrainState(Drainable::Draining);
411 return child_drain_count + 1;
412 }
413
414 drainManager = NULL;
415 setDrainState(Drainable::Drained);
416 return child_drain_count;
417}
418
419void
420RubyPort::M5Port::hitCallback(PacketPtr pkt)
421{
422 bool needsResponse = pkt->needsResponse();
423
424 //
425 // Unless specified at configuraiton, all responses except failed SC
426 // and Flush operations access M5 physical memory.
427 //
428 bool accessPhysMem = access_phys_mem;
429
430 if (pkt->isLLSC()) {
431 if (pkt->isWrite()) {
432 if (pkt->req->getExtraData() != 0) {
433 //
434 // Successful SC packets convert to normal writes
435 //
436 pkt->convertScToWrite();
437 } else {
438 //
439 // Failed SC packets don't access physical memory and thus
440 // the RubyPort itself must convert it to a response.
441 //
442 accessPhysMem = false;
443 }
444 } else {
445 //
446 // All LL packets convert to normal loads so that M5 PhysMem does
447 // not lock the blocks.
448 //
449 pkt->convertLlToRead();
450 }
451 }
452
453 //
454 // Flush requests don't access physical memory
455 //
456 if (pkt->isFlush()) {
457 accessPhysMem = false;
458 }
459
460 DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse);
461
462 if (accessPhysMem) {
463 ruby_port->system->getPhysMem().access(pkt);
464 } else if (needsResponse) {
465 pkt->makeResponse();
466 }
467
468 // turn packet around to go back to requester if response expected
469 if (needsResponse) {
470 DPRINTF(RubyPort, "Sending packet back over port\n");
471 // send next cycle
472 schedTimingResp(pkt, curTick() + g_system_ptr->clockPeriod());
473 } else {
474 delete pkt;
475 }
476 DPRINTF(RubyPort, "Hit callback done!\n");
477}
478
479AddrRangeList
480RubyPort::M5Port::getAddrRanges() const
481{
482 // at the moment the assumption is that the master does not care
483 AddrRangeList ranges;
484 return ranges;
485}
486
487bool
488RubyPort::M5Port::isPhysMemAddress(Addr addr)
489{
490 return ruby_port->system->isMemAddr(addr);
491}
492
493unsigned
494RubyPort::M5Port::deviceBlockSize() const
495{
496 return (unsigned) RubySystem::getBlockSizeBytes();
497}
498
499void
500RubyPort::ruby_eviction_callback(const Address& address)
501{
502 DPRINTF(RubyPort, "Sending invalidations.\n");
503 // should this really be using funcMasterId?
504 Request req(address.getAddress(), 0, 0, Request::funcMasterId);
505 for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) {
506 // check if the connected master port is snooping
507 if ((*p)->isSnooping()) {
508 Packet *pkt = new Packet(&req, MemCmd::InvalidationReq);
509 // send as a snoop request
510 (*p)->sendTimingSnoopReq(pkt);
511 }
512 }
513}
| 306 delete senderState;
307
308 port->hitCallback(pkt);
309
310 //
311 // If we had to stall the M5Ports, wake them up because the sequencer
312 // likely has free resources now.
313 //
314 if (waitingOnSequencer) {
315 //
316 // Record the current list of ports to retry on a temporary list before
317 // calling sendRetry on those ports. sendRetry will cause an
318 // immediate retry, which may result in the ports being put back on the
319 // list. Therefore we want to clear the retryList before calling
320 // sendRetry.
321 //
322 std::list<M5Port*> curRetryList(retryList);
323
324 retryList.clear();
325 waitingOnSequencer = false;
326
327 for (std::list<M5Port*>::iterator i = curRetryList.begin();
328 i != curRetryList.end(); ++i) {
329 DPRINTF(RubyPort,
330 "Sequencer may now be free. SendRetry to port %s\n",
331 (*i)->name());
332 (*i)->onRetryList(false);
333 (*i)->sendRetry();
334 }
335 }
336
337 testDrainComplete();
338}
339
340void
341RubyPort::testDrainComplete()
342{
343 //If we weren't able to drain before, we might be able to now.
344 if (drainManager != NULL) {
345 unsigned int drainCount = outstandingCount();
346 DPRINTF(Drain, "Drain count: %u\n", drainCount);
347 if (drainCount == 0) {
348 DPRINTF(Drain, "RubyPort done draining, signaling drain done\n");
349 drainManager->signalDrainDone();
350 // Clear the drain manager once we're done with it.
351 drainManager = NULL;
352 }
353 }
354}
355
356unsigned int
357RubyPort::getChildDrainCount(DrainManager *dm)
358{
359 int count = 0;
360
361 if (pio_port.isConnected()) {
362 count += pio_port.drain(dm);
363 DPRINTF(Config, "count after pio check %d\n", count);
364 }
365
366 for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) {
367 count += (*p)->drain(dm);
368 DPRINTF(Config, "count after slave port check %d\n", count);
369 }
370
371 for (std::vector<PioPort*>::iterator p = master_ports.begin();
372 p != master_ports.end(); ++p) {
373 count += (*p)->drain(dm);
374 DPRINTF(Config, "count after master port check %d\n", count);
375 }
376
377 DPRINTF(Config, "final count %d\n", count);
378
379 return count;
380}
381
382unsigned int
383RubyPort::drain(DrainManager *dm)
384{
385 if (isDeadlockEventScheduled()) {
386 descheduleDeadlockEvent();
387 }
388
389 //
390 // If the RubyPort is not empty, then it needs to clear all outstanding
391 // requests before it should call drainManager->signalDrainDone()
392 //
393 DPRINTF(Config, "outstanding count %d\n", outstandingCount());
394 bool need_drain = outstandingCount() > 0;
395
396 //
397 // Also, get the number of child ports that will also need to clear
398 // their buffered requests before they call drainManager->signalDrainDone()
399 //
400 unsigned int child_drain_count = getChildDrainCount(dm);
401
402 // Set status
403 if (need_drain) {
404 drainManager = dm;
405
406 DPRINTF(Drain, "RubyPort not drained\n");
407 setDrainState(Drainable::Draining);
408 return child_drain_count + 1;
409 }
410
411 drainManager = NULL;
412 setDrainState(Drainable::Drained);
413 return child_drain_count;
414}
415
416void
417RubyPort::M5Port::hitCallback(PacketPtr pkt)
418{
419 bool needsResponse = pkt->needsResponse();
420
421 //
422 // Unless specified at configuraiton, all responses except failed SC
423 // and Flush operations access M5 physical memory.
424 //
425 bool accessPhysMem = access_phys_mem;
426
427 if (pkt->isLLSC()) {
428 if (pkt->isWrite()) {
429 if (pkt->req->getExtraData() != 0) {
430 //
431 // Successful SC packets convert to normal writes
432 //
433 pkt->convertScToWrite();
434 } else {
435 //
436 // Failed SC packets don't access physical memory and thus
437 // the RubyPort itself must convert it to a response.
438 //
439 accessPhysMem = false;
440 }
441 } else {
442 //
443 // All LL packets convert to normal loads so that M5 PhysMem does
444 // not lock the blocks.
445 //
446 pkt->convertLlToRead();
447 }
448 }
449
450 //
451 // Flush requests don't access physical memory
452 //
453 if (pkt->isFlush()) {
454 accessPhysMem = false;
455 }
456
457 DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse);
458
459 if (accessPhysMem) {
460 ruby_port->system->getPhysMem().access(pkt);
461 } else if (needsResponse) {
462 pkt->makeResponse();
463 }
464
465 // turn packet around to go back to requester if response expected
466 if (needsResponse) {
467 DPRINTF(RubyPort, "Sending packet back over port\n");
468 // send next cycle
469 schedTimingResp(pkt, curTick() + g_system_ptr->clockPeriod());
470 } else {
471 delete pkt;
472 }
473 DPRINTF(RubyPort, "Hit callback done!\n");
474}
475
476AddrRangeList
477RubyPort::M5Port::getAddrRanges() const
478{
479 // at the moment the assumption is that the master does not care
480 AddrRangeList ranges;
481 return ranges;
482}
483
484bool
485RubyPort::M5Port::isPhysMemAddress(Addr addr)
486{
487 return ruby_port->system->isMemAddr(addr);
488}
489
490unsigned
491RubyPort::M5Port::deviceBlockSize() const
492{
493 return (unsigned) RubySystem::getBlockSizeBytes();
494}
495
496void
497RubyPort::ruby_eviction_callback(const Address& address)
498{
499 DPRINTF(RubyPort, "Sending invalidations.\n");
500 // should this really be using funcMasterId?
501 Request req(address.getAddress(), 0, 0, Request::funcMasterId);
502 for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) {
503 // check if the connected master port is snooping
504 if ((*p)->isSnooping()) {
505 Packet *pkt = new Packet(&req, MemCmd::InvalidationReq);
506 // send as a snoop request
507 (*p)->sendTimingSnoopReq(pkt);
508 }
509 }
510}
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