1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 Advanced Micro Devices, Inc.
15 * Copyright (c) 2011 Mark D. Hill and David A. Wood
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
42#include "cpu/testers/rubytest/RubyTester.hh"
43#include "debug/Config.hh"
44#include "debug/Drain.hh"
45#include "debug/Ruby.hh"
46#include "mem/protocol/AccessPermission.hh"
47#include "mem/ruby/slicc_interface/AbstractController.hh"
48#include "mem/ruby/system/RubyPort.hh"
49#include "sim/system.hh"
50
51RubyPort::RubyPort(const Params *p)
52 : MemObject(p), m_version(p->version), m_controller(NULL),
53 m_mandatory_q_ptr(NULL),
54 pio_port(csprintf("%s-pio-port", name()), this),
55 m_usingRubyTester(p->using_ruby_tester), m_request_cnt(0),
56 drainManager(NULL), ruby_system(p->ruby_system), system(p->system),
57 waitingOnSequencer(false), access_phys_mem(p->access_phys_mem)
58{
59 assert(m_version != -1);
60
61 // create the slave ports based on the number of connected ports
62 for (size_t i = 0; i < p->port_slave_connection_count; ++i) {
63 slave_ports.push_back(new M5Port(csprintf("%s-slave%d", name(), i),
64 this, ruby_system, access_phys_mem));
65 }
66
67 // create the master ports based on the number of connected ports
68 for (size_t i = 0; i < p->port_master_connection_count; ++i) {
69 master_ports.push_back(new PioPort(csprintf("%s-master%d", name(), i),
70 this));
71 }
72}
73
74void
75RubyPort::init()
76{
77 assert(m_controller != NULL);
78 m_mandatory_q_ptr = m_controller->getMandatoryQueue();
| 1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 Advanced Micro Devices, Inc.
15 * Copyright (c) 2011 Mark D. Hill and David A. Wood
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
42#include "cpu/testers/rubytest/RubyTester.hh"
43#include "debug/Config.hh"
44#include "debug/Drain.hh"
45#include "debug/Ruby.hh"
46#include "mem/protocol/AccessPermission.hh"
47#include "mem/ruby/slicc_interface/AbstractController.hh"
48#include "mem/ruby/system/RubyPort.hh"
49#include "sim/system.hh"
50
51RubyPort::RubyPort(const Params *p)
52 : MemObject(p), m_version(p->version), m_controller(NULL),
53 m_mandatory_q_ptr(NULL),
54 pio_port(csprintf("%s-pio-port", name()), this),
55 m_usingRubyTester(p->using_ruby_tester), m_request_cnt(0),
56 drainManager(NULL), ruby_system(p->ruby_system), system(p->system),
57 waitingOnSequencer(false), access_phys_mem(p->access_phys_mem)
58{
59 assert(m_version != -1);
60
61 // create the slave ports based on the number of connected ports
62 for (size_t i = 0; i < p->port_slave_connection_count; ++i) {
63 slave_ports.push_back(new M5Port(csprintf("%s-slave%d", name(), i),
64 this, ruby_system, access_phys_mem));
65 }
66
67 // create the master ports based on the number of connected ports
68 for (size_t i = 0; i < p->port_master_connection_count; ++i) {
69 master_ports.push_back(new PioPort(csprintf("%s-master%d", name(), i),
70 this));
71 }
72}
73
74void
75RubyPort::init()
76{
77 assert(m_controller != NULL);
78 m_mandatory_q_ptr = m_controller->getMandatoryQueue();
|
79}
80
81BaseMasterPort &
82RubyPort::getMasterPort(const std::string &if_name, PortID idx)
83{
84 if (if_name == "pio_port") {
85 return pio_port;
86 }
87
88 // used by the x86 CPUs to connect the interrupt PIO and interrupt slave
89 // port
90 if (if_name != "master") {
91 // pass it along to our super class
92 return MemObject::getMasterPort(if_name, idx);
93 } else {
94 if (idx >= static_cast<PortID>(master_ports.size())) {
95 panic("RubyPort::getMasterPort: unknown index %d\n", idx);
96 }
97
98 return *master_ports[idx];
99 }
100}
101
102BaseSlavePort &
103RubyPort::getSlavePort(const std::string &if_name, PortID idx)
104{
105 // used by the CPUs to connect the caches to the interconnect, and
106 // for the x86 case also the interrupt master
107 if (if_name != "slave") {
108 // pass it along to our super class
109 return MemObject::getSlavePort(if_name, idx);
110 } else {
111 if (idx >= static_cast<PortID>(slave_ports.size())) {
112 panic("RubyPort::getSlavePort: unknown index %d\n", idx);
113 }
114
115 return *slave_ports[idx];
116 }
117}
118
119RubyPort::PioPort::PioPort(const std::string &_name,
120 RubyPort *_port)
121 : QueuedMasterPort(_name, _port, queue), queue(*_port, *this),
122 ruby_port(_port)
123{
124 DPRINTF(RubyPort, "creating master port on ruby sequencer %s\n", _name);
125}
126
127RubyPort::M5Port::M5Port(const std::string &_name, RubyPort *_port,
128 RubySystem *_system, bool _access_phys_mem)
129 : QueuedSlavePort(_name, _port, queue), queue(*_port, *this),
130 ruby_port(_port), ruby_system(_system),
131 _onRetryList(false), access_phys_mem(_access_phys_mem)
132{
133 DPRINTF(RubyPort, "creating slave port on ruby sequencer %s\n", _name);
134}
135
136Tick
137RubyPort::M5Port::recvAtomic(PacketPtr pkt)
138{
139 panic("RubyPort::M5Port::recvAtomic() not implemented!\n");
140 return 0;
141}
142
143
144bool
145RubyPort::PioPort::recvTimingResp(PacketPtr pkt)
146{
147 // In FS mode, ruby memory will receive pio responses from devices
148 // and it must forward these responses back to the particular CPU.
149 DPRINTF(RubyPort, "Pio response for address %#x\n", pkt->getAddr());
150
151 // First we must retrieve the request port from the sender State
152 RubyPort::SenderState *senderState =
153 safe_cast<RubyPort::SenderState *>(pkt->senderState);
154 M5Port *port = senderState->port;
155 assert(port != NULL);
156
157 // pop the sender state from the packet
158 pkt->senderState = senderState->saved;
159 delete senderState;
160
161 port->sendTimingResp(pkt);
162
163 return true;
164}
165
166bool
167RubyPort::M5Port::recvTimingReq(PacketPtr pkt)
168{
169 DPRINTF(RubyPort,
170 "Timing access caught for address %#x\n", pkt->getAddr());
171
172 //dsm: based on SimpleTimingPort::recvTimingReq(pkt);
173
174 // The received packets should only be M5 requests, which should never
175 // get nacked. There used to be code to hanldle nacks here, but
176 // I'm pretty sure it didn't work correctly with the drain code,
177 // so that would need to be fixed if we ever added it back.
178
179 if (pkt->memInhibitAsserted()) {
180 warn("memInhibitAsserted???");
181 // snooper will supply based on copy of packet
182 // still target's responsibility to delete packet
183 delete pkt;
184 return true;
185 }
186
187 // Save the port in the sender state object to be used later to
188 // route the response
189 pkt->senderState = new SenderState(this, pkt->senderState);
190
191 // Check for pio requests and directly send them to the dedicated
192 // pio port.
193 if (!isPhysMemAddress(pkt->getAddr())) {
194 assert(ruby_port->pio_port.isConnected());
195 DPRINTF(RubyPort,
196 "Request for address 0x%#x is assumed to be a pio request\n",
197 pkt->getAddr());
198
199 // send next cycle
200 ruby_port->pio_port.schedTimingReq(pkt,
201 curTick() + g_system_ptr->clockPeriod());
202 return true;
203 }
204
205 assert(Address(pkt->getAddr()).getOffset() + pkt->getSize() <=
206 RubySystem::getBlockSizeBytes());
207
208 // Submit the ruby request
209 RequestStatus requestStatus = ruby_port->makeRequest(pkt);
210
211 // If the request successfully issued then we should return true.
212 // Otherwise, we need to delete the senderStatus we just created and return
213 // false.
214 if (requestStatus == RequestStatus_Issued) {
215 DPRINTF(RubyPort, "Request %#x issued\n", pkt->getAddr());
216 return true;
217 }
218
219 //
220 // Unless one is using the ruby tester, record the stalled M5 port for
221 // later retry when the sequencer becomes free.
222 //
223 if (!ruby_port->m_usingRubyTester) {
224 ruby_port->addToRetryList(this);
225 }
226
227 DPRINTF(RubyPort,
228 "Request for address %#x did not issue because %s\n",
229 pkt->getAddr(), RequestStatus_to_string(requestStatus));
230
231 SenderState* senderState = safe_cast<SenderState*>(pkt->senderState);
232 pkt->senderState = senderState->saved;
233 delete senderState;
234 return false;
235}
236
237void
238RubyPort::M5Port::recvFunctional(PacketPtr pkt)
239{
240 DPRINTF(RubyPort, "Functional access caught for address %#x\n",
241 pkt->getAddr());
242
243 // Check for pio requests and directly send them to the dedicated
244 // pio port.
245 if (!isPhysMemAddress(pkt->getAddr())) {
246 assert(ruby_port->pio_port.isConnected());
247 DPRINTF(RubyPort, "Request for address 0x%#x is a pio request\n",
248 pkt->getAddr());
249 panic("RubyPort::PioPort::recvFunctional() not implemented!\n");
250 }
251
252 assert(pkt->getAddr() + pkt->getSize() <=
253 line_address(Address(pkt->getAddr())).getAddress() +
254 RubySystem::getBlockSizeBytes());
255
256 bool accessSucceeded = false;
257 bool needsResponse = pkt->needsResponse();
258
259 // Do the functional access on ruby memory
260 if (pkt->isRead()) {
261 accessSucceeded = ruby_system->functionalRead(pkt);
262 } else if (pkt->isWrite()) {
263 accessSucceeded = ruby_system->functionalWrite(pkt);
264 } else {
265 panic("RubyPort: unsupported functional command %s\n",
266 pkt->cmdString());
267 }
268
269 // Unless the requester explicitly said otherwise, generate an error if
270 // the functional request failed
271 if (!accessSucceeded && !pkt->suppressFuncError()) {
272 fatal("Ruby functional %s failed for address %#x\n",
273 pkt->isWrite() ? "write" : "read", pkt->getAddr());
274 }
275
276 if (access_phys_mem) {
277 // The attached physmem contains the official version of data.
278 // The following command performs the real functional access.
279 // This line should be removed once Ruby supplies the official version
280 // of data.
281 ruby_port->system->getPhysMem().functionalAccess(pkt);
282 }
283
284 // turn packet around to go back to requester if response expected
285 if (needsResponse) {
286 pkt->setFunctionalResponseStatus(accessSucceeded);
287
288 // @todo There should not be a reverse call since the response is
289 // communicated through the packet pointer
290 // DPRINTF(RubyPort, "Sending packet back over port\n");
291 // sendFunctional(pkt);
292 }
293 DPRINTF(RubyPort, "Functional access %s!\n",
294 accessSucceeded ? "successful":"failed");
295}
296
297void
298RubyPort::ruby_hit_callback(PacketPtr pkt)
299{
300 // Retrieve the request port from the sender State
301 RubyPort::SenderState *senderState =
302 safe_cast<RubyPort::SenderState *>(pkt->senderState);
303 M5Port *port = senderState->port;
304 assert(port != NULL);
305
306 // pop the sender state from the packet
307 pkt->senderState = senderState->saved;
308 delete senderState;
309
310 port->hitCallback(pkt);
311
312 //
313 // If we had to stall the M5Ports, wake them up because the sequencer
314 // likely has free resources now.
315 //
316 if (waitingOnSequencer) {
317 //
318 // Record the current list of ports to retry on a temporary list before
319 // calling sendRetry on those ports. sendRetry will cause an
320 // immediate retry, which may result in the ports being put back on the
321 // list. Therefore we want to clear the retryList before calling
322 // sendRetry.
323 //
324 std::list<M5Port*> curRetryList(retryList);
325
326 retryList.clear();
327 waitingOnSequencer = false;
328
329 for (std::list<M5Port*>::iterator i = curRetryList.begin();
330 i != curRetryList.end(); ++i) {
331 DPRINTF(RubyPort,
332 "Sequencer may now be free. SendRetry to port %s\n",
333 (*i)->name());
334 (*i)->onRetryList(false);
335 (*i)->sendRetry();
336 }
337 }
338
339 testDrainComplete();
340}
341
342void
343RubyPort::testDrainComplete()
344{
345 //If we weren't able to drain before, we might be able to now.
346 if (drainManager != NULL) {
347 unsigned int drainCount = outstandingCount();
348 DPRINTF(Drain, "Drain count: %u\n", drainCount);
349 if (drainCount == 0) {
350 DPRINTF(Drain, "RubyPort done draining, signaling drain done\n");
351 drainManager->signalDrainDone();
352 // Clear the drain manager once we're done with it.
353 drainManager = NULL;
354 }
355 }
356}
357
358unsigned int
359RubyPort::getChildDrainCount(DrainManager *dm)
360{
361 int count = 0;
362
363 if (pio_port.isConnected()) {
364 count += pio_port.drain(dm);
365 DPRINTF(Config, "count after pio check %d\n", count);
366 }
367
368 for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) {
369 count += (*p)->drain(dm);
370 DPRINTF(Config, "count after slave port check %d\n", count);
371 }
372
373 for (std::vector<PioPort*>::iterator p = master_ports.begin();
374 p != master_ports.end(); ++p) {
375 count += (*p)->drain(dm);
376 DPRINTF(Config, "count after master port check %d\n", count);
377 }
378
379 DPRINTF(Config, "final count %d\n", count);
380
381 return count;
382}
383
384unsigned int
385RubyPort::drain(DrainManager *dm)
386{
387 if (isDeadlockEventScheduled()) {
388 descheduleDeadlockEvent();
389 }
390
391 //
392 // If the RubyPort is not empty, then it needs to clear all outstanding
393 // requests before it should call drainManager->signalDrainDone()
394 //
395 DPRINTF(Config, "outstanding count %d\n", outstandingCount());
396 bool need_drain = outstandingCount() > 0;
397
398 //
399 // Also, get the number of child ports that will also need to clear
400 // their buffered requests before they call drainManager->signalDrainDone()
401 //
402 unsigned int child_drain_count = getChildDrainCount(dm);
403
404 // Set status
405 if (need_drain) {
406 drainManager = dm;
407
408 DPRINTF(Drain, "RubyPort not drained\n");
409 setDrainState(Drainable::Draining);
410 return child_drain_count + 1;
411 }
412
413 drainManager = NULL;
414 setDrainState(Drainable::Drained);
415 return child_drain_count;
416}
417
418void
419RubyPort::M5Port::hitCallback(PacketPtr pkt)
420{
421 bool needsResponse = pkt->needsResponse();
422
423 //
424 // Unless specified at configuraiton, all responses except failed SC
425 // and Flush operations access M5 physical memory.
426 //
427 bool accessPhysMem = access_phys_mem;
428
429 if (pkt->isLLSC()) {
430 if (pkt->isWrite()) {
431 if (pkt->req->getExtraData() != 0) {
432 //
433 // Successful SC packets convert to normal writes
434 //
435 pkt->convertScToWrite();
436 } else {
437 //
438 // Failed SC packets don't access physical memory and thus
439 // the RubyPort itself must convert it to a response.
440 //
441 accessPhysMem = false;
442 }
443 } else {
444 //
445 // All LL packets convert to normal loads so that M5 PhysMem does
446 // not lock the blocks.
447 //
448 pkt->convertLlToRead();
449 }
450 }
451
452 //
453 // Flush requests don't access physical memory
454 //
455 if (pkt->isFlush()) {
456 accessPhysMem = false;
457 }
458
459 DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse);
460
461 if (accessPhysMem) {
462 ruby_port->system->getPhysMem().access(pkt);
463 } else if (needsResponse) {
464 pkt->makeResponse();
465 }
466
467 // turn packet around to go back to requester if response expected
468 if (needsResponse) {
469 DPRINTF(RubyPort, "Sending packet back over port\n");
470 // send next cycle
471 schedTimingResp(pkt, curTick() + g_system_ptr->clockPeriod());
472 } else {
473 delete pkt;
474 }
475 DPRINTF(RubyPort, "Hit callback done!\n");
476}
477
478AddrRangeList
479RubyPort::M5Port::getAddrRanges() const
480{
481 // at the moment the assumption is that the master does not care
482 AddrRangeList ranges;
483 return ranges;
484}
485
486bool
487RubyPort::M5Port::isPhysMemAddress(Addr addr)
488{
489 return ruby_port->system->isMemAddr(addr);
490}
491
492unsigned
493RubyPort::M5Port::deviceBlockSize() const
494{
495 return (unsigned) RubySystem::getBlockSizeBytes();
496}
497
498void
499RubyPort::ruby_eviction_callback(const Address& address)
500{
501 DPRINTF(RubyPort, "Sending invalidations.\n");
502 // should this really be using funcMasterId?
503 Request req(address.getAddress(), 0, 0, Request::funcMasterId);
504 for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) {
505 // check if the connected master port is snooping
506 if ((*p)->isSnooping()) {
507 Packet *pkt = new Packet(&req, MemCmd::InvalidationReq);
508 // send as a snoop request
509 (*p)->sendTimingSnoopReq(pkt);
510 }
511 }
512}
| 80}
81
82BaseMasterPort &
83RubyPort::getMasterPort(const std::string &if_name, PortID idx)
84{
85 if (if_name == "pio_port") {
86 return pio_port;
87 }
88
89 // used by the x86 CPUs to connect the interrupt PIO and interrupt slave
90 // port
91 if (if_name != "master") {
92 // pass it along to our super class
93 return MemObject::getMasterPort(if_name, idx);
94 } else {
95 if (idx >= static_cast<PortID>(master_ports.size())) {
96 panic("RubyPort::getMasterPort: unknown index %d\n", idx);
97 }
98
99 return *master_ports[idx];
100 }
101}
102
103BaseSlavePort &
104RubyPort::getSlavePort(const std::string &if_name, PortID idx)
105{
106 // used by the CPUs to connect the caches to the interconnect, and
107 // for the x86 case also the interrupt master
108 if (if_name != "slave") {
109 // pass it along to our super class
110 return MemObject::getSlavePort(if_name, idx);
111 } else {
112 if (idx >= static_cast<PortID>(slave_ports.size())) {
113 panic("RubyPort::getSlavePort: unknown index %d\n", idx);
114 }
115
116 return *slave_ports[idx];
117 }
118}
119
120RubyPort::PioPort::PioPort(const std::string &_name,
121 RubyPort *_port)
122 : QueuedMasterPort(_name, _port, queue), queue(*_port, *this),
123 ruby_port(_port)
124{
125 DPRINTF(RubyPort, "creating master port on ruby sequencer %s\n", _name);
126}
127
128RubyPort::M5Port::M5Port(const std::string &_name, RubyPort *_port,
129 RubySystem *_system, bool _access_phys_mem)
130 : QueuedSlavePort(_name, _port, queue), queue(*_port, *this),
131 ruby_port(_port), ruby_system(_system),
132 _onRetryList(false), access_phys_mem(_access_phys_mem)
133{
134 DPRINTF(RubyPort, "creating slave port on ruby sequencer %s\n", _name);
135}
136
137Tick
138RubyPort::M5Port::recvAtomic(PacketPtr pkt)
139{
140 panic("RubyPort::M5Port::recvAtomic() not implemented!\n");
141 return 0;
142}
143
144
145bool
146RubyPort::PioPort::recvTimingResp(PacketPtr pkt)
147{
148 // In FS mode, ruby memory will receive pio responses from devices
149 // and it must forward these responses back to the particular CPU.
150 DPRINTF(RubyPort, "Pio response for address %#x\n", pkt->getAddr());
151
152 // First we must retrieve the request port from the sender State
153 RubyPort::SenderState *senderState =
154 safe_cast<RubyPort::SenderState *>(pkt->senderState);
155 M5Port *port = senderState->port;
156 assert(port != NULL);
157
158 // pop the sender state from the packet
159 pkt->senderState = senderState->saved;
160 delete senderState;
161
162 port->sendTimingResp(pkt);
163
164 return true;
165}
166
167bool
168RubyPort::M5Port::recvTimingReq(PacketPtr pkt)
169{
170 DPRINTF(RubyPort,
171 "Timing access caught for address %#x\n", pkt->getAddr());
172
173 //dsm: based on SimpleTimingPort::recvTimingReq(pkt);
174
175 // The received packets should only be M5 requests, which should never
176 // get nacked. There used to be code to hanldle nacks here, but
177 // I'm pretty sure it didn't work correctly with the drain code,
178 // so that would need to be fixed if we ever added it back.
179
180 if (pkt->memInhibitAsserted()) {
181 warn("memInhibitAsserted???");
182 // snooper will supply based on copy of packet
183 // still target's responsibility to delete packet
184 delete pkt;
185 return true;
186 }
187
188 // Save the port in the sender state object to be used later to
189 // route the response
190 pkt->senderState = new SenderState(this, pkt->senderState);
191
192 // Check for pio requests and directly send them to the dedicated
193 // pio port.
194 if (!isPhysMemAddress(pkt->getAddr())) {
195 assert(ruby_port->pio_port.isConnected());
196 DPRINTF(RubyPort,
197 "Request for address 0x%#x is assumed to be a pio request\n",
198 pkt->getAddr());
199
200 // send next cycle
201 ruby_port->pio_port.schedTimingReq(pkt,
202 curTick() + g_system_ptr->clockPeriod());
203 return true;
204 }
205
206 assert(Address(pkt->getAddr()).getOffset() + pkt->getSize() <=
207 RubySystem::getBlockSizeBytes());
208
209 // Submit the ruby request
210 RequestStatus requestStatus = ruby_port->makeRequest(pkt);
211
212 // If the request successfully issued then we should return true.
213 // Otherwise, we need to delete the senderStatus we just created and return
214 // false.
215 if (requestStatus == RequestStatus_Issued) {
216 DPRINTF(RubyPort, "Request %#x issued\n", pkt->getAddr());
217 return true;
218 }
219
220 //
221 // Unless one is using the ruby tester, record the stalled M5 port for
222 // later retry when the sequencer becomes free.
223 //
224 if (!ruby_port->m_usingRubyTester) {
225 ruby_port->addToRetryList(this);
226 }
227
228 DPRINTF(RubyPort,
229 "Request for address %#x did not issue because %s\n",
230 pkt->getAddr(), RequestStatus_to_string(requestStatus));
231
232 SenderState* senderState = safe_cast<SenderState*>(pkt->senderState);
233 pkt->senderState = senderState->saved;
234 delete senderState;
235 return false;
236}
237
238void
239RubyPort::M5Port::recvFunctional(PacketPtr pkt)
240{
241 DPRINTF(RubyPort, "Functional access caught for address %#x\n",
242 pkt->getAddr());
243
244 // Check for pio requests and directly send them to the dedicated
245 // pio port.
246 if (!isPhysMemAddress(pkt->getAddr())) {
247 assert(ruby_port->pio_port.isConnected());
248 DPRINTF(RubyPort, "Request for address 0x%#x is a pio request\n",
249 pkt->getAddr());
250 panic("RubyPort::PioPort::recvFunctional() not implemented!\n");
251 }
252
253 assert(pkt->getAddr() + pkt->getSize() <=
254 line_address(Address(pkt->getAddr())).getAddress() +
255 RubySystem::getBlockSizeBytes());
256
257 bool accessSucceeded = false;
258 bool needsResponse = pkt->needsResponse();
259
260 // Do the functional access on ruby memory
261 if (pkt->isRead()) {
262 accessSucceeded = ruby_system->functionalRead(pkt);
263 } else if (pkt->isWrite()) {
264 accessSucceeded = ruby_system->functionalWrite(pkt);
265 } else {
266 panic("RubyPort: unsupported functional command %s\n",
267 pkt->cmdString());
268 }
269
270 // Unless the requester explicitly said otherwise, generate an error if
271 // the functional request failed
272 if (!accessSucceeded && !pkt->suppressFuncError()) {
273 fatal("Ruby functional %s failed for address %#x\n",
274 pkt->isWrite() ? "write" : "read", pkt->getAddr());
275 }
276
277 if (access_phys_mem) {
278 // The attached physmem contains the official version of data.
279 // The following command performs the real functional access.
280 // This line should be removed once Ruby supplies the official version
281 // of data.
282 ruby_port->system->getPhysMem().functionalAccess(pkt);
283 }
284
285 // turn packet around to go back to requester if response expected
286 if (needsResponse) {
287 pkt->setFunctionalResponseStatus(accessSucceeded);
288
289 // @todo There should not be a reverse call since the response is
290 // communicated through the packet pointer
291 // DPRINTF(RubyPort, "Sending packet back over port\n");
292 // sendFunctional(pkt);
293 }
294 DPRINTF(RubyPort, "Functional access %s!\n",
295 accessSucceeded ? "successful":"failed");
296}
297
298void
299RubyPort::ruby_hit_callback(PacketPtr pkt)
300{
301 // Retrieve the request port from the sender State
302 RubyPort::SenderState *senderState =
303 safe_cast<RubyPort::SenderState *>(pkt->senderState);
304 M5Port *port = senderState->port;
305 assert(port != NULL);
306
307 // pop the sender state from the packet
308 pkt->senderState = senderState->saved;
309 delete senderState;
310
311 port->hitCallback(pkt);
312
313 //
314 // If we had to stall the M5Ports, wake them up because the sequencer
315 // likely has free resources now.
316 //
317 if (waitingOnSequencer) {
318 //
319 // Record the current list of ports to retry on a temporary list before
320 // calling sendRetry on those ports. sendRetry will cause an
321 // immediate retry, which may result in the ports being put back on the
322 // list. Therefore we want to clear the retryList before calling
323 // sendRetry.
324 //
325 std::list<M5Port*> curRetryList(retryList);
326
327 retryList.clear();
328 waitingOnSequencer = false;
329
330 for (std::list<M5Port*>::iterator i = curRetryList.begin();
331 i != curRetryList.end(); ++i) {
332 DPRINTF(RubyPort,
333 "Sequencer may now be free. SendRetry to port %s\n",
334 (*i)->name());
335 (*i)->onRetryList(false);
336 (*i)->sendRetry();
337 }
338 }
339
340 testDrainComplete();
341}
342
343void
344RubyPort::testDrainComplete()
345{
346 //If we weren't able to drain before, we might be able to now.
347 if (drainManager != NULL) {
348 unsigned int drainCount = outstandingCount();
349 DPRINTF(Drain, "Drain count: %u\n", drainCount);
350 if (drainCount == 0) {
351 DPRINTF(Drain, "RubyPort done draining, signaling drain done\n");
352 drainManager->signalDrainDone();
353 // Clear the drain manager once we're done with it.
354 drainManager = NULL;
355 }
356 }
357}
358
359unsigned int
360RubyPort::getChildDrainCount(DrainManager *dm)
361{
362 int count = 0;
363
364 if (pio_port.isConnected()) {
365 count += pio_port.drain(dm);
366 DPRINTF(Config, "count after pio check %d\n", count);
367 }
368
369 for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) {
370 count += (*p)->drain(dm);
371 DPRINTF(Config, "count after slave port check %d\n", count);
372 }
373
374 for (std::vector<PioPort*>::iterator p = master_ports.begin();
375 p != master_ports.end(); ++p) {
376 count += (*p)->drain(dm);
377 DPRINTF(Config, "count after master port check %d\n", count);
378 }
379
380 DPRINTF(Config, "final count %d\n", count);
381
382 return count;
383}
384
385unsigned int
386RubyPort::drain(DrainManager *dm)
387{
388 if (isDeadlockEventScheduled()) {
389 descheduleDeadlockEvent();
390 }
391
392 //
393 // If the RubyPort is not empty, then it needs to clear all outstanding
394 // requests before it should call drainManager->signalDrainDone()
395 //
396 DPRINTF(Config, "outstanding count %d\n", outstandingCount());
397 bool need_drain = outstandingCount() > 0;
398
399 //
400 // Also, get the number of child ports that will also need to clear
401 // their buffered requests before they call drainManager->signalDrainDone()
402 //
403 unsigned int child_drain_count = getChildDrainCount(dm);
404
405 // Set status
406 if (need_drain) {
407 drainManager = dm;
408
409 DPRINTF(Drain, "RubyPort not drained\n");
410 setDrainState(Drainable::Draining);
411 return child_drain_count + 1;
412 }
413
414 drainManager = NULL;
415 setDrainState(Drainable::Drained);
416 return child_drain_count;
417}
418
419void
420RubyPort::M5Port::hitCallback(PacketPtr pkt)
421{
422 bool needsResponse = pkt->needsResponse();
423
424 //
425 // Unless specified at configuraiton, all responses except failed SC
426 // and Flush operations access M5 physical memory.
427 //
428 bool accessPhysMem = access_phys_mem;
429
430 if (pkt->isLLSC()) {
431 if (pkt->isWrite()) {
432 if (pkt->req->getExtraData() != 0) {
433 //
434 // Successful SC packets convert to normal writes
435 //
436 pkt->convertScToWrite();
437 } else {
438 //
439 // Failed SC packets don't access physical memory and thus
440 // the RubyPort itself must convert it to a response.
441 //
442 accessPhysMem = false;
443 }
444 } else {
445 //
446 // All LL packets convert to normal loads so that M5 PhysMem does
447 // not lock the blocks.
448 //
449 pkt->convertLlToRead();
450 }
451 }
452
453 //
454 // Flush requests don't access physical memory
455 //
456 if (pkt->isFlush()) {
457 accessPhysMem = false;
458 }
459
460 DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse);
461
462 if (accessPhysMem) {
463 ruby_port->system->getPhysMem().access(pkt);
464 } else if (needsResponse) {
465 pkt->makeResponse();
466 }
467
468 // turn packet around to go back to requester if response expected
469 if (needsResponse) {
470 DPRINTF(RubyPort, "Sending packet back over port\n");
471 // send next cycle
472 schedTimingResp(pkt, curTick() + g_system_ptr->clockPeriod());
473 } else {
474 delete pkt;
475 }
476 DPRINTF(RubyPort, "Hit callback done!\n");
477}
478
479AddrRangeList
480RubyPort::M5Port::getAddrRanges() const
481{
482 // at the moment the assumption is that the master does not care
483 AddrRangeList ranges;
484 return ranges;
485}
486
487bool
488RubyPort::M5Port::isPhysMemAddress(Addr addr)
489{
490 return ruby_port->system->isMemAddr(addr);
491}
492
493unsigned
494RubyPort::M5Port::deviceBlockSize() const
495{
496 return (unsigned) RubySystem::getBlockSizeBytes();
497}
498
499void
500RubyPort::ruby_eviction_callback(const Address& address)
501{
502 DPRINTF(RubyPort, "Sending invalidations.\n");
503 // should this really be using funcMasterId?
504 Request req(address.getAddress(), 0, 0, Request::funcMasterId);
505 for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) {
506 // check if the connected master port is snooping
507 if ((*p)->isSnooping()) {
508 Packet *pkt = new Packet(&req, MemCmd::InvalidationReq);
509 // send as a snoop request
510 (*p)->sendTimingSnoopReq(pkt);
511 }
512 }
513}
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