1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 Advanced Micro Devices, Inc.
15 * Copyright (c) 2011 Mark D. Hill and David A. Wood
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
42#include "cpu/testers/rubytest/RubyTester.hh"
43#include "debug/Config.hh"
44#include "debug/Ruby.hh"
45#include "mem/protocol/AccessPermission.hh"
46#include "mem/ruby/slicc_interface/AbstractController.hh"
47#include "mem/ruby/system/RubyPort.hh"
48#include "sim/system.hh"
49
50RubyPort::RubyPort(const Params *p)
51 : MemObject(p), m_version(p->version), m_controller(NULL),
52 m_mandatory_q_ptr(NULL),
53 pio_port(csprintf("%s-pio-port", name()), this),
54 m_usingRubyTester(p->using_ruby_tester), m_request_cnt(0),
55 drainEvent(NULL), ruby_system(p->ruby_system), system(p->system),
56 waitingOnSequencer(false), access_phys_mem(p->access_phys_mem)
57{
58 assert(m_version != -1);
59
60 // create the slave ports based on the number of connected ports
61 for (size_t i = 0; i < p->port_slave_connection_count; ++i) {
62 slave_ports.push_back(new M5Port(csprintf("%s-slave%d", name(), i),
63 this, ruby_system, access_phys_mem));
64 }
65
66 // create the master ports based on the number of connected ports
67 for (size_t i = 0; i < p->port_master_connection_count; ++i) {
68 master_ports.push_back(new PioPort(csprintf("%s-master%d", name(), i),
69 this));
70 }
71}
72
73void
74RubyPort::init()
75{
76 assert(m_controller != NULL);
77 m_mandatory_q_ptr = m_controller->getMandatoryQueue();
78}
79
80MasterPort &
81RubyPort::getMasterPort(const std::string &if_name, int idx)
82{
83 if (if_name == "pio_port") {
84 return pio_port;
85 }
86
87 // used by the x86 CPUs to connect the interrupt PIO and interrupt slave
88 // port
89 if (if_name != "master") {
90 // pass it along to our super class
91 return MemObject::getMasterPort(if_name, idx);
92 } else {
93 if (idx >= static_cast<int>(master_ports.size())) {
94 panic("RubyPort::getMasterPort: unknown index %d\n", idx);
95 }
96
97 return *master_ports[idx];
98 }
99}
100
101SlavePort &
102RubyPort::getSlavePort(const std::string &if_name, int idx)
103{
104 // used by the CPUs to connect the caches to the interconnect, and
105 // for the x86 case also the interrupt master
106 if (if_name != "slave") {
107 // pass it along to our super class
108 return MemObject::getSlavePort(if_name, idx);
109 } else {
110 if (idx >= static_cast<int>(slave_ports.size())) {
111 panic("RubyPort::getSlavePort: unknown index %d\n", idx);
112 }
113
114 return *slave_ports[idx];
115 }
116}
117
118RubyPort::PioPort::PioPort(const std::string &_name,
119 RubyPort *_port)
120 : QueuedMasterPort(_name, _port, queue), queue(*_port, *this),
121 ruby_port(_port)
122{
123 DPRINTF(RubyPort, "creating master port on ruby sequencer %s\n", _name);
124}
125
126RubyPort::M5Port::M5Port(const std::string &_name, RubyPort *_port,
127 RubySystem *_system, bool _access_phys_mem)
128 : QueuedSlavePort(_name, _port, queue), queue(*_port, *this),
129 ruby_port(_port), ruby_system(_system),
130 _onRetryList(false), access_phys_mem(_access_phys_mem)
131{
132 DPRINTF(RubyPort, "creating slave port on ruby sequencer %s\n", _name);
133}
134
135Tick
136RubyPort::M5Port::recvAtomic(PacketPtr pkt)
137{
138 panic("RubyPort::M5Port::recvAtomic() not implemented!\n");
139 return 0;
140}
141
142
143bool
144RubyPort::PioPort::recvTimingResp(PacketPtr pkt)
145{
146 // In FS mode, ruby memory will receive pio responses from devices
147 // and it must forward these responses back to the particular CPU.
148 DPRINTF(RubyPort, "Pio response for address %#x\n", pkt->getAddr());
149
150 // First we must retrieve the request port from the sender State
151 RubyPort::SenderState *senderState =
152 safe_cast<RubyPort::SenderState *>(pkt->senderState);
153 M5Port *port = senderState->port;
154 assert(port != NULL);
155
156 // pop the sender state from the packet
157 pkt->senderState = senderState->saved;
158 delete senderState;
159
160 port->sendTimingResp(pkt);
161
162 return true;
163}
164
165bool
166RubyPort::M5Port::recvTimingReq(PacketPtr pkt)
167{
168 DPRINTF(RubyPort,
169 "Timing access caught for address %#x\n", pkt->getAddr());
170
171 //dsm: based on SimpleTimingPort::recvTimingReq(pkt);
172
173 // The received packets should only be M5 requests, which should never
174 // get nacked. There used to be code to hanldle nacks here, but
175 // I'm pretty sure it didn't work correctly with the drain code,
176 // so that would need to be fixed if we ever added it back.
177
178 if (pkt->memInhibitAsserted()) {
179 warn("memInhibitAsserted???");
180 // snooper will supply based on copy of packet
181 // still target's responsibility to delete packet
182 delete pkt;
183 return true;
184 }
185
186 // Save the port in the sender state object to be used later to
187 // route the response
188 pkt->senderState = new SenderState(this, pkt->senderState);
189
190 // Check for pio requests and directly send them to the dedicated
191 // pio port.
192 if (!isPhysMemAddress(pkt->getAddr())) {
193 assert(ruby_port->pio_port.isConnected());
194 DPRINTF(RubyPort,
195 "Request for address 0x%#x is assumed to be a pio request\n",
196 pkt->getAddr());
197
198 return ruby_port->pio_port.sendNextCycle(pkt);
199 }
200
201 assert(Address(pkt->getAddr()).getOffset() + pkt->getSize() <=
202 RubySystem::getBlockSizeBytes());
203
204 // Submit the ruby request
205 RequestStatus requestStatus = ruby_port->makeRequest(pkt);
206
207 // If the request successfully issued then we should return true.
208 // Otherwise, we need to delete the senderStatus we just created and return
209 // false.
210 if (requestStatus == RequestStatus_Issued) {
211 DPRINTF(RubyPort, "Request %#x issued\n", pkt->getAddr());
212 return true;
213 }
214
215 //
216 // Unless one is using the ruby tester, record the stalled M5 port for
217 // later retry when the sequencer becomes free.
218 //
219 if (!ruby_port->m_usingRubyTester) {
220 ruby_port->addToRetryList(this);
221 }
222
223 DPRINTF(RubyPort,
224 "Request for address %#x did not issue because %s\n",
225 pkt->getAddr(), RequestStatus_to_string(requestStatus));
226
227 SenderState* senderState = safe_cast<SenderState*>(pkt->senderState);
228 pkt->senderState = senderState->saved;
229 delete senderState;
230 return false;
231}
232
233bool
234RubyPort::M5Port::doFunctionalRead(PacketPtr pkt)
235{
236 Address address(pkt->getAddr());
237 Address line_address(address);
238 line_address.makeLineAddress();
239
240 AccessPermission access_perm = AccessPermission_NotPresent;
241 int num_controllers = ruby_system->m_abs_cntrl_vec.size();
242
243 DPRINTF(RubyPort, "Functional Read request for %s\n",address);
244
245 unsigned int num_ro = 0;
246 unsigned int num_rw = 0;
247 unsigned int num_busy = 0;
248 unsigned int num_backing_store = 0;
249 unsigned int num_invalid = 0;
250
251 // In this loop we count the number of controllers that have the given
252 // address in read only, read write and busy states.
253 for (int i = 0; i < num_controllers; ++i) {
254 access_perm = ruby_system->m_abs_cntrl_vec[i]->
255 getAccessPermission(line_address);
256 if (access_perm == AccessPermission_Read_Only)
257 num_ro++;
258 else if (access_perm == AccessPermission_Read_Write)
259 num_rw++;
260 else if (access_perm == AccessPermission_Busy)
261 num_busy++;
262 else if (access_perm == AccessPermission_Backing_Store)
263 // See RubySlicc_Exports.sm for details, but Backing_Store is meant
264 // to represent blocks in memory *for Broadcast/Snooping protocols*,
265 // where memory has no idea whether it has an exclusive copy of data
266 // or not.
267 num_backing_store++;
268 else if (access_perm == AccessPermission_Invalid ||
269 access_perm == AccessPermission_NotPresent)
270 num_invalid++;
271 }
272 assert(num_rw <= 1);
273
274 uint8* data = pkt->getPtr<uint8_t>(true);
275 unsigned int size_in_bytes = pkt->getSize();
276 unsigned startByte = address.getAddress() - line_address.getAddress();
277
278 // This if case is meant to capture what happens in a Broadcast/Snoop
279 // protocol where the block does not exist in the cache hierarchy. You
280 // only want to read from the Backing_Store memory if there is no copy in
281 // the cache hierarchy, otherwise you want to try to read the RO or RW
282 // copies existing in the cache hierarchy (covered by the else statement).
283 // The reason is because the Backing_Store memory could easily be stale, if
284 // there are copies floating around the cache hierarchy, so you want to read
285 // it only if it's not in the cache hierarchy at all.
286 if (num_invalid == (num_controllers - 1) &&
287 num_backing_store == 1)
288 {
289 DPRINTF(RubyPort, "only copy in Backing_Store memory, read from it\n");
290 for (int i = 0; i < num_controllers; ++i) {
291 access_perm = ruby_system->m_abs_cntrl_vec[i]
292 ->getAccessPermission(line_address);
293 if (access_perm == AccessPermission_Backing_Store) {
294 DataBlock& block = ruby_system->m_abs_cntrl_vec[i]
295 ->getDataBlock(line_address);
296
297 DPRINTF(RubyPort, "reading from %s block %s\n",
298 ruby_system->m_abs_cntrl_vec[i]->name(), block);
299 for (unsigned i = 0; i < size_in_bytes; ++i) {
300 data[i] = block.getByte(i + startByte);
301 }
302 return true;
303 }
304 }
305 } else {
306 // In Broadcast/Snoop protocols, this covers if you know the block
307 // exists somewhere in the caching hierarchy, then you want to read any
308 // valid RO or RW block. In directory protocols, same thing, you want
309 // to read any valid readable copy of the block.
310 DPRINTF(RubyPort, "num_busy = %d, num_ro = %d, num_rw = %d\n",
311 num_busy, num_ro, num_rw);
312 // In this loop, we try to figure which controller has a read only or
313 // a read write copy of the given address. Any valid copy would suffice
314 // for a functional read.
315 for(int i = 0;i < num_controllers;++i) {
316 access_perm = ruby_system->m_abs_cntrl_vec[i]
317 ->getAccessPermission(line_address);
318 if(access_perm == AccessPermission_Read_Only ||
319 access_perm == AccessPermission_Read_Write)
320 {
321 DataBlock& block = ruby_system->m_abs_cntrl_vec[i]
322 ->getDataBlock(line_address);
323
324 DPRINTF(RubyPort, "reading from %s block %s\n",
325 ruby_system->m_abs_cntrl_vec[i]->name(), block);
326 for (unsigned i = 0; i < size_in_bytes; ++i) {
327 data[i] = block.getByte(i + startByte);
328 }
329 return true;
330 }
331 }
332 }
333 return false;
334}
335
336bool
337RubyPort::M5Port::doFunctionalWrite(PacketPtr pkt)
338{
339 Address addr(pkt->getAddr());
340 Address line_addr = line_address(addr);
341 AccessPermission access_perm = AccessPermission_NotPresent;
342 int num_controllers = ruby_system->m_abs_cntrl_vec.size();
343
344 DPRINTF(RubyPort, "Functional Write request for %s\n",addr);
345
346 unsigned int num_ro = 0;
347 unsigned int num_rw = 0;
348 unsigned int num_busy = 0;
349 unsigned int num_backing_store = 0;
350 unsigned int num_invalid = 0;
351
352 // In this loop we count the number of controllers that have the given
353 // address in read only, read write and busy states.
354 for(int i = 0;i < num_controllers;++i) {
355 access_perm = ruby_system->m_abs_cntrl_vec[i]->
356 getAccessPermission(line_addr);
357 if (access_perm == AccessPermission_Read_Only)
358 num_ro++;
359 else if (access_perm == AccessPermission_Read_Write)
360 num_rw++;
361 else if (access_perm == AccessPermission_Busy)
362 num_busy++;
363 else if (access_perm == AccessPermission_Backing_Store)
364 // See RubySlicc_Exports.sm for details, but Backing_Store is meant
365 // to represent blocks in memory *for Broadcast/Snooping protocols*,
366 // where memory has no idea whether it has an exclusive copy of data
367 // or not.
368 num_backing_store++;
369 else if (access_perm == AccessPermission_Invalid ||
370 access_perm == AccessPermission_NotPresent)
371 num_invalid++;
372 }
373
374 // If the number of read write copies is more than 1, then there is bug in
375 // coherence protocol. Otherwise, if all copies are in stable states, i.e.
376 // num_busy == 0, we update all the copies. If there is at least one copy
377 // in busy state, then we check if there is read write copy. If yes, then
378 // also we let the access go through. Or, if there is no copy in the cache
379 // hierarchy at all, we still want to do the write to the memory
380 // (Backing_Store) instead of failing.
381
382 DPRINTF(RubyPort, "num_busy = %d, num_ro = %d, num_rw = %d\n",
383 num_busy, num_ro, num_rw);
384 assert(num_rw <= 1);
385
386 uint8* data = pkt->getPtr<uint8_t>(true);
387 unsigned int size_in_bytes = pkt->getSize();
388 unsigned startByte = addr.getAddress() - line_addr.getAddress();
389
390 if ((num_busy == 0 && num_ro > 0) || num_rw == 1 ||
391 (num_invalid == (num_controllers - 1) && num_backing_store == 1))
392 {
393 for(int i = 0; i < num_controllers;++i) {
394 access_perm = ruby_system->m_abs_cntrl_vec[i]->
395 getAccessPermission(line_addr);
396 if(access_perm == AccessPermission_Read_Only ||
397 access_perm == AccessPermission_Read_Write||
398 access_perm == AccessPermission_Maybe_Stale ||
399 access_perm == AccessPermission_Backing_Store)
400 {
401 DataBlock& block = ruby_system->m_abs_cntrl_vec[i]
402 ->getDataBlock(line_addr);
403
404 DPRINTF(RubyPort, "%s\n",block);
405 for (unsigned i = 0; i < size_in_bytes; ++i) {
406 block.setByte(i + startByte, data[i]);
407 }
408 DPRINTF(RubyPort, "%s\n",block);
409 }
410 }
411 return true;
412 }
413 return false;
414}
415
416void
417RubyPort::M5Port::recvFunctional(PacketPtr pkt)
418{
419 DPRINTF(RubyPort, "Functional access caught for address %#x\n",
420 pkt->getAddr());
421
422 // Check for pio requests and directly send them to the dedicated
423 // pio port.
424 if (!isPhysMemAddress(pkt->getAddr())) {
425 assert(ruby_port->pio_port.isConnected());
426 DPRINTF(RubyPort, "Request for address 0x%#x is a pio request\n",
427 pkt->getAddr());
428 panic("RubyPort::PioPort::recvFunctional() not implemented!\n");
429 }
430
431 assert(pkt->getAddr() + pkt->getSize() <=
432 line_address(Address(pkt->getAddr())).getAddress() +
433 RubySystem::getBlockSizeBytes());
434
435 bool accessSucceeded = false;
436 bool needsResponse = pkt->needsResponse();
437
438 // Do the functional access on ruby memory
439 if (pkt->isRead()) {
440 accessSucceeded = doFunctionalRead(pkt);
441 } else if (pkt->isWrite()) {
442 accessSucceeded = doFunctionalWrite(pkt);
443 } else {
444 panic("RubyPort: unsupported functional command %s\n",
445 pkt->cmdString());
446 }
447
448 // Unless the requester explicitly said otherwise, generate an error if
449 // the functional request failed
450 if (!accessSucceeded && !pkt->suppressFuncError()) {
451 fatal("Ruby functional %s failed for address %#x\n",
452 pkt->isWrite() ? "write" : "read", pkt->getAddr());
453 }
454
455 if (access_phys_mem) {
456 // The attached physmem contains the official version of data.
457 // The following command performs the real functional access.
458 // This line should be removed once Ruby supplies the official version
459 // of data.
460 ruby_port->system->getPhysMem().functionalAccess(pkt);
461 }
462
463 // turn packet around to go back to requester if response expected
464 if (needsResponse) {
465 pkt->setFunctionalResponseStatus(accessSucceeded);
466
467 // @todo There should not be a reverse call since the response is
468 // communicated through the packet pointer
469 // DPRINTF(RubyPort, "Sending packet back over port\n");
470 // sendFunctional(pkt);
471 }
472 DPRINTF(RubyPort, "Functional access %s!\n",
473 accessSucceeded ? "successful":"failed");
474}
475
476void
477RubyPort::ruby_hit_callback(PacketPtr pkt)
478{
479 // Retrieve the request port from the sender State
480 RubyPort::SenderState *senderState =
481 safe_cast<RubyPort::SenderState *>(pkt->senderState);
482 M5Port *port = senderState->port;
483 assert(port != NULL);
484
485 // pop the sender state from the packet
486 pkt->senderState = senderState->saved;
487 delete senderState;
488
489 port->hitCallback(pkt);
490
491 //
492 // If we had to stall the M5Ports, wake them up because the sequencer
493 // likely has free resources now.
494 //
495 if (waitingOnSequencer) {
496 //
497 // Record the current list of ports to retry on a temporary list before
498 // calling sendRetry on those ports. sendRetry will cause an
499 // immediate retry, which may result in the ports being put back on the
500 // list. Therefore we want to clear the retryList before calling
501 // sendRetry.
502 //
503 std::list<M5Port*> curRetryList(retryList);
504
505 retryList.clear();
506 waitingOnSequencer = false;
507
508 for (std::list<M5Port*>::iterator i = curRetryList.begin();
509 i != curRetryList.end(); ++i) {
510 DPRINTF(RubyPort,
511 "Sequencer may now be free. SendRetry to port %s\n",
512 (*i)->name());
513 (*i)->onRetryList(false);
514 (*i)->sendRetry();
515 }
516 }
517
518 testDrainComplete();
519}
520
521void
522RubyPort::testDrainComplete()
523{
524 //If we weren't able to drain before, we might be able to now.
525 if (drainEvent != NULL) {
526 unsigned int drainCount = getDrainCount(drainEvent);
527 DPRINTF(Config, "Drain count: %u\n", drainCount);
528 if (drainCount == 0) {
529 drainEvent->process();
530 // Clear the drain event once we're done with it.
531 drainEvent = NULL;
532 }
533 }
534}
535
536unsigned int
537RubyPort::getDrainCount(Event *de)
538{
539 int count = 0;
540 //
541 // If the sequencer is not empty, then requests need to drain.
542 // The outstandingCount is the number of requests outstanding and thus the
543 // number of times M5's timing port will process the drain event.
544 //
545 count += outstandingCount();
546
547 DPRINTF(Config, "outstanding count %d\n", outstandingCount());
548
549 // To simplify the draining process, the sequencer's deadlock detection
550 // event should have been descheduled.
551 assert(isDeadlockEventScheduled() == false);
552
553 if (pio_port.isConnected()) {
554 count += pio_port.drain(de);
555 DPRINTF(Config, "count after pio check %d\n", count);
556 }
557
558 for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) {
559 count += (*p)->drain(de);
560 DPRINTF(Config, "count after slave port check %d\n", count);
561 }
562
563 for (std::vector<PioPort*>::iterator p = master_ports.begin();
564 p != master_ports.end(); ++p) {
565 count += (*p)->drain(de);
566 DPRINTF(Config, "count after master port check %d\n", count);
567 }
568
569 DPRINTF(Config, "final count %d\n", count);
570
571 return count;
572}
573
574unsigned int
575RubyPort::drain(Event *de)
576{
577 if (isDeadlockEventScheduled()) {
578 descheduleDeadlockEvent();
579 }
580
581 int count = getDrainCount(de);
582
583 // Set status
584 if (count != 0) {
585 drainEvent = de;
586
587 changeState(SimObject::Draining);
588 return count;
589 }
590
591 changeState(SimObject::Drained);
592 return 0;
593}
594
595void
596RubyPort::M5Port::hitCallback(PacketPtr pkt)
597{
598 bool needsResponse = pkt->needsResponse();
599
600 //
601 // Unless specified at configuraiton, all responses except failed SC
602 // and Flush operations access M5 physical memory.
603 //
604 bool accessPhysMem = access_phys_mem;
605
606 if (pkt->isLLSC()) {
607 if (pkt->isWrite()) {
608 if (pkt->req->getExtraData() != 0) {
609 //
610 // Successful SC packets convert to normal writes
611 //
612 pkt->convertScToWrite();
613 } else {
614 //
615 // Failed SC packets don't access physical memory and thus
616 // the RubyPort itself must convert it to a response.
617 //
618 accessPhysMem = false;
619 }
620 } else {
621 //
622 // All LL packets convert to normal loads so that M5 PhysMem does
623 // not lock the blocks.
624 //
625 pkt->convertLlToRead();
626 }
627 }
628
629 //
630 // Flush requests don't access physical memory
631 //
632 if (pkt->isFlush()) {
633 accessPhysMem = false;
634 }
635
636 DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse);
637
638 if (accessPhysMem) {
639 ruby_port->system->getPhysMem().access(pkt);
640 } else if (needsResponse) {
641 pkt->makeResponse();
642 }
643
644 // turn packet around to go back to requester if response expected
645 if (needsResponse) {
646 DPRINTF(RubyPort, "Sending packet back over port\n");
647 sendNextCycle(pkt);
648 } else {
649 delete pkt;
650 }
651 DPRINTF(RubyPort, "Hit callback done!\n");
652}
653
654bool
655RubyPort::M5Port::sendNextCycle(PacketPtr pkt, bool send_as_snoop)
656{
657 //minimum latency, must be > 0
658 queue.schedSendTiming(pkt, curTick() + (1 * g_eventQueue_ptr->getClock()),
659 send_as_snoop);
660 return true;
661}
662
663bool
664RubyPort::PioPort::sendNextCycle(PacketPtr pkt)
665{
666 //minimum latency, must be > 0
667 queue.schedSendTiming(pkt, curTick() + (1 * g_eventQueue_ptr->getClock()));
668 return true;
669}
670
671AddrRangeList
672RubyPort::M5Port::getAddrRanges()
673{
674 // at the moment the assumption is that the master does not care
675 AddrRangeList ranges;
676 return ranges;
677}
678
679bool
680RubyPort::M5Port::isPhysMemAddress(Addr addr)
681{
682 return ruby_port->system->isMemAddr(addr);
683}
684
685unsigned
686RubyPort::M5Port::deviceBlockSize() const
687{
688 return (unsigned) RubySystem::getBlockSizeBytes();
689}
690
691void
692RubyPort::ruby_eviction_callback(const Address& address)
693{
694 DPRINTF(RubyPort, "Sending invalidations.\n");
695 // should this really be using funcMasterId?
696 Request req(address.getAddress(), 0, 0, Request::funcMasterId);
697 for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) {
| 1/*
2 * Copyright (c) 2012 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 Advanced Micro Devices, Inc.
15 * Copyright (c) 2011 Mark D. Hill and David A. Wood
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
42#include "cpu/testers/rubytest/RubyTester.hh"
43#include "debug/Config.hh"
44#include "debug/Ruby.hh"
45#include "mem/protocol/AccessPermission.hh"
46#include "mem/ruby/slicc_interface/AbstractController.hh"
47#include "mem/ruby/system/RubyPort.hh"
48#include "sim/system.hh"
49
50RubyPort::RubyPort(const Params *p)
51 : MemObject(p), m_version(p->version), m_controller(NULL),
52 m_mandatory_q_ptr(NULL),
53 pio_port(csprintf("%s-pio-port", name()), this),
54 m_usingRubyTester(p->using_ruby_tester), m_request_cnt(0),
55 drainEvent(NULL), ruby_system(p->ruby_system), system(p->system),
56 waitingOnSequencer(false), access_phys_mem(p->access_phys_mem)
57{
58 assert(m_version != -1);
59
60 // create the slave ports based on the number of connected ports
61 for (size_t i = 0; i < p->port_slave_connection_count; ++i) {
62 slave_ports.push_back(new M5Port(csprintf("%s-slave%d", name(), i),
63 this, ruby_system, access_phys_mem));
64 }
65
66 // create the master ports based on the number of connected ports
67 for (size_t i = 0; i < p->port_master_connection_count; ++i) {
68 master_ports.push_back(new PioPort(csprintf("%s-master%d", name(), i),
69 this));
70 }
71}
72
73void
74RubyPort::init()
75{
76 assert(m_controller != NULL);
77 m_mandatory_q_ptr = m_controller->getMandatoryQueue();
78}
79
80MasterPort &
81RubyPort::getMasterPort(const std::string &if_name, int idx)
82{
83 if (if_name == "pio_port") {
84 return pio_port;
85 }
86
87 // used by the x86 CPUs to connect the interrupt PIO and interrupt slave
88 // port
89 if (if_name != "master") {
90 // pass it along to our super class
91 return MemObject::getMasterPort(if_name, idx);
92 } else {
93 if (idx >= static_cast<int>(master_ports.size())) {
94 panic("RubyPort::getMasterPort: unknown index %d\n", idx);
95 }
96
97 return *master_ports[idx];
98 }
99}
100
101SlavePort &
102RubyPort::getSlavePort(const std::string &if_name, int idx)
103{
104 // used by the CPUs to connect the caches to the interconnect, and
105 // for the x86 case also the interrupt master
106 if (if_name != "slave") {
107 // pass it along to our super class
108 return MemObject::getSlavePort(if_name, idx);
109 } else {
110 if (idx >= static_cast<int>(slave_ports.size())) {
111 panic("RubyPort::getSlavePort: unknown index %d\n", idx);
112 }
113
114 return *slave_ports[idx];
115 }
116}
117
118RubyPort::PioPort::PioPort(const std::string &_name,
119 RubyPort *_port)
120 : QueuedMasterPort(_name, _port, queue), queue(*_port, *this),
121 ruby_port(_port)
122{
123 DPRINTF(RubyPort, "creating master port on ruby sequencer %s\n", _name);
124}
125
126RubyPort::M5Port::M5Port(const std::string &_name, RubyPort *_port,
127 RubySystem *_system, bool _access_phys_mem)
128 : QueuedSlavePort(_name, _port, queue), queue(*_port, *this),
129 ruby_port(_port), ruby_system(_system),
130 _onRetryList(false), access_phys_mem(_access_phys_mem)
131{
132 DPRINTF(RubyPort, "creating slave port on ruby sequencer %s\n", _name);
133}
134
135Tick
136RubyPort::M5Port::recvAtomic(PacketPtr pkt)
137{
138 panic("RubyPort::M5Port::recvAtomic() not implemented!\n");
139 return 0;
140}
141
142
143bool
144RubyPort::PioPort::recvTimingResp(PacketPtr pkt)
145{
146 // In FS mode, ruby memory will receive pio responses from devices
147 // and it must forward these responses back to the particular CPU.
148 DPRINTF(RubyPort, "Pio response for address %#x\n", pkt->getAddr());
149
150 // First we must retrieve the request port from the sender State
151 RubyPort::SenderState *senderState =
152 safe_cast<RubyPort::SenderState *>(pkt->senderState);
153 M5Port *port = senderState->port;
154 assert(port != NULL);
155
156 // pop the sender state from the packet
157 pkt->senderState = senderState->saved;
158 delete senderState;
159
160 port->sendTimingResp(pkt);
161
162 return true;
163}
164
165bool
166RubyPort::M5Port::recvTimingReq(PacketPtr pkt)
167{
168 DPRINTF(RubyPort,
169 "Timing access caught for address %#x\n", pkt->getAddr());
170
171 //dsm: based on SimpleTimingPort::recvTimingReq(pkt);
172
173 // The received packets should only be M5 requests, which should never
174 // get nacked. There used to be code to hanldle nacks here, but
175 // I'm pretty sure it didn't work correctly with the drain code,
176 // so that would need to be fixed if we ever added it back.
177
178 if (pkt->memInhibitAsserted()) {
179 warn("memInhibitAsserted???");
180 // snooper will supply based on copy of packet
181 // still target's responsibility to delete packet
182 delete pkt;
183 return true;
184 }
185
186 // Save the port in the sender state object to be used later to
187 // route the response
188 pkt->senderState = new SenderState(this, pkt->senderState);
189
190 // Check for pio requests and directly send them to the dedicated
191 // pio port.
192 if (!isPhysMemAddress(pkt->getAddr())) {
193 assert(ruby_port->pio_port.isConnected());
194 DPRINTF(RubyPort,
195 "Request for address 0x%#x is assumed to be a pio request\n",
196 pkt->getAddr());
197
198 return ruby_port->pio_port.sendNextCycle(pkt);
199 }
200
201 assert(Address(pkt->getAddr()).getOffset() + pkt->getSize() <=
202 RubySystem::getBlockSizeBytes());
203
204 // Submit the ruby request
205 RequestStatus requestStatus = ruby_port->makeRequest(pkt);
206
207 // If the request successfully issued then we should return true.
208 // Otherwise, we need to delete the senderStatus we just created and return
209 // false.
210 if (requestStatus == RequestStatus_Issued) {
211 DPRINTF(RubyPort, "Request %#x issued\n", pkt->getAddr());
212 return true;
213 }
214
215 //
216 // Unless one is using the ruby tester, record the stalled M5 port for
217 // later retry when the sequencer becomes free.
218 //
219 if (!ruby_port->m_usingRubyTester) {
220 ruby_port->addToRetryList(this);
221 }
222
223 DPRINTF(RubyPort,
224 "Request for address %#x did not issue because %s\n",
225 pkt->getAddr(), RequestStatus_to_string(requestStatus));
226
227 SenderState* senderState = safe_cast<SenderState*>(pkt->senderState);
228 pkt->senderState = senderState->saved;
229 delete senderState;
230 return false;
231}
232
233bool
234RubyPort::M5Port::doFunctionalRead(PacketPtr pkt)
235{
236 Address address(pkt->getAddr());
237 Address line_address(address);
238 line_address.makeLineAddress();
239
240 AccessPermission access_perm = AccessPermission_NotPresent;
241 int num_controllers = ruby_system->m_abs_cntrl_vec.size();
242
243 DPRINTF(RubyPort, "Functional Read request for %s\n",address);
244
245 unsigned int num_ro = 0;
246 unsigned int num_rw = 0;
247 unsigned int num_busy = 0;
248 unsigned int num_backing_store = 0;
249 unsigned int num_invalid = 0;
250
251 // In this loop we count the number of controllers that have the given
252 // address in read only, read write and busy states.
253 for (int i = 0; i < num_controllers; ++i) {
254 access_perm = ruby_system->m_abs_cntrl_vec[i]->
255 getAccessPermission(line_address);
256 if (access_perm == AccessPermission_Read_Only)
257 num_ro++;
258 else if (access_perm == AccessPermission_Read_Write)
259 num_rw++;
260 else if (access_perm == AccessPermission_Busy)
261 num_busy++;
262 else if (access_perm == AccessPermission_Backing_Store)
263 // See RubySlicc_Exports.sm for details, but Backing_Store is meant
264 // to represent blocks in memory *for Broadcast/Snooping protocols*,
265 // where memory has no idea whether it has an exclusive copy of data
266 // or not.
267 num_backing_store++;
268 else if (access_perm == AccessPermission_Invalid ||
269 access_perm == AccessPermission_NotPresent)
270 num_invalid++;
271 }
272 assert(num_rw <= 1);
273
274 uint8* data = pkt->getPtr<uint8_t>(true);
275 unsigned int size_in_bytes = pkt->getSize();
276 unsigned startByte = address.getAddress() - line_address.getAddress();
277
278 // This if case is meant to capture what happens in a Broadcast/Snoop
279 // protocol where the block does not exist in the cache hierarchy. You
280 // only want to read from the Backing_Store memory if there is no copy in
281 // the cache hierarchy, otherwise you want to try to read the RO or RW
282 // copies existing in the cache hierarchy (covered by the else statement).
283 // The reason is because the Backing_Store memory could easily be stale, if
284 // there are copies floating around the cache hierarchy, so you want to read
285 // it only if it's not in the cache hierarchy at all.
286 if (num_invalid == (num_controllers - 1) &&
287 num_backing_store == 1)
288 {
289 DPRINTF(RubyPort, "only copy in Backing_Store memory, read from it\n");
290 for (int i = 0; i < num_controllers; ++i) {
291 access_perm = ruby_system->m_abs_cntrl_vec[i]
292 ->getAccessPermission(line_address);
293 if (access_perm == AccessPermission_Backing_Store) {
294 DataBlock& block = ruby_system->m_abs_cntrl_vec[i]
295 ->getDataBlock(line_address);
296
297 DPRINTF(RubyPort, "reading from %s block %s\n",
298 ruby_system->m_abs_cntrl_vec[i]->name(), block);
299 for (unsigned i = 0; i < size_in_bytes; ++i) {
300 data[i] = block.getByte(i + startByte);
301 }
302 return true;
303 }
304 }
305 } else {
306 // In Broadcast/Snoop protocols, this covers if you know the block
307 // exists somewhere in the caching hierarchy, then you want to read any
308 // valid RO or RW block. In directory protocols, same thing, you want
309 // to read any valid readable copy of the block.
310 DPRINTF(RubyPort, "num_busy = %d, num_ro = %d, num_rw = %d\n",
311 num_busy, num_ro, num_rw);
312 // In this loop, we try to figure which controller has a read only or
313 // a read write copy of the given address. Any valid copy would suffice
314 // for a functional read.
315 for(int i = 0;i < num_controllers;++i) {
316 access_perm = ruby_system->m_abs_cntrl_vec[i]
317 ->getAccessPermission(line_address);
318 if(access_perm == AccessPermission_Read_Only ||
319 access_perm == AccessPermission_Read_Write)
320 {
321 DataBlock& block = ruby_system->m_abs_cntrl_vec[i]
322 ->getDataBlock(line_address);
323
324 DPRINTF(RubyPort, "reading from %s block %s\n",
325 ruby_system->m_abs_cntrl_vec[i]->name(), block);
326 for (unsigned i = 0; i < size_in_bytes; ++i) {
327 data[i] = block.getByte(i + startByte);
328 }
329 return true;
330 }
331 }
332 }
333 return false;
334}
335
336bool
337RubyPort::M5Port::doFunctionalWrite(PacketPtr pkt)
338{
339 Address addr(pkt->getAddr());
340 Address line_addr = line_address(addr);
341 AccessPermission access_perm = AccessPermission_NotPresent;
342 int num_controllers = ruby_system->m_abs_cntrl_vec.size();
343
344 DPRINTF(RubyPort, "Functional Write request for %s\n",addr);
345
346 unsigned int num_ro = 0;
347 unsigned int num_rw = 0;
348 unsigned int num_busy = 0;
349 unsigned int num_backing_store = 0;
350 unsigned int num_invalid = 0;
351
352 // In this loop we count the number of controllers that have the given
353 // address in read only, read write and busy states.
354 for(int i = 0;i < num_controllers;++i) {
355 access_perm = ruby_system->m_abs_cntrl_vec[i]->
356 getAccessPermission(line_addr);
357 if (access_perm == AccessPermission_Read_Only)
358 num_ro++;
359 else if (access_perm == AccessPermission_Read_Write)
360 num_rw++;
361 else if (access_perm == AccessPermission_Busy)
362 num_busy++;
363 else if (access_perm == AccessPermission_Backing_Store)
364 // See RubySlicc_Exports.sm for details, but Backing_Store is meant
365 // to represent blocks in memory *for Broadcast/Snooping protocols*,
366 // where memory has no idea whether it has an exclusive copy of data
367 // or not.
368 num_backing_store++;
369 else if (access_perm == AccessPermission_Invalid ||
370 access_perm == AccessPermission_NotPresent)
371 num_invalid++;
372 }
373
374 // If the number of read write copies is more than 1, then there is bug in
375 // coherence protocol. Otherwise, if all copies are in stable states, i.e.
376 // num_busy == 0, we update all the copies. If there is at least one copy
377 // in busy state, then we check if there is read write copy. If yes, then
378 // also we let the access go through. Or, if there is no copy in the cache
379 // hierarchy at all, we still want to do the write to the memory
380 // (Backing_Store) instead of failing.
381
382 DPRINTF(RubyPort, "num_busy = %d, num_ro = %d, num_rw = %d\n",
383 num_busy, num_ro, num_rw);
384 assert(num_rw <= 1);
385
386 uint8* data = pkt->getPtr<uint8_t>(true);
387 unsigned int size_in_bytes = pkt->getSize();
388 unsigned startByte = addr.getAddress() - line_addr.getAddress();
389
390 if ((num_busy == 0 && num_ro > 0) || num_rw == 1 ||
391 (num_invalid == (num_controllers - 1) && num_backing_store == 1))
392 {
393 for(int i = 0; i < num_controllers;++i) {
394 access_perm = ruby_system->m_abs_cntrl_vec[i]->
395 getAccessPermission(line_addr);
396 if(access_perm == AccessPermission_Read_Only ||
397 access_perm == AccessPermission_Read_Write||
398 access_perm == AccessPermission_Maybe_Stale ||
399 access_perm == AccessPermission_Backing_Store)
400 {
401 DataBlock& block = ruby_system->m_abs_cntrl_vec[i]
402 ->getDataBlock(line_addr);
403
404 DPRINTF(RubyPort, "%s\n",block);
405 for (unsigned i = 0; i < size_in_bytes; ++i) {
406 block.setByte(i + startByte, data[i]);
407 }
408 DPRINTF(RubyPort, "%s\n",block);
409 }
410 }
411 return true;
412 }
413 return false;
414}
415
416void
417RubyPort::M5Port::recvFunctional(PacketPtr pkt)
418{
419 DPRINTF(RubyPort, "Functional access caught for address %#x\n",
420 pkt->getAddr());
421
422 // Check for pio requests and directly send them to the dedicated
423 // pio port.
424 if (!isPhysMemAddress(pkt->getAddr())) {
425 assert(ruby_port->pio_port.isConnected());
426 DPRINTF(RubyPort, "Request for address 0x%#x is a pio request\n",
427 pkt->getAddr());
428 panic("RubyPort::PioPort::recvFunctional() not implemented!\n");
429 }
430
431 assert(pkt->getAddr() + pkt->getSize() <=
432 line_address(Address(pkt->getAddr())).getAddress() +
433 RubySystem::getBlockSizeBytes());
434
435 bool accessSucceeded = false;
436 bool needsResponse = pkt->needsResponse();
437
438 // Do the functional access on ruby memory
439 if (pkt->isRead()) {
440 accessSucceeded = doFunctionalRead(pkt);
441 } else if (pkt->isWrite()) {
442 accessSucceeded = doFunctionalWrite(pkt);
443 } else {
444 panic("RubyPort: unsupported functional command %s\n",
445 pkt->cmdString());
446 }
447
448 // Unless the requester explicitly said otherwise, generate an error if
449 // the functional request failed
450 if (!accessSucceeded && !pkt->suppressFuncError()) {
451 fatal("Ruby functional %s failed for address %#x\n",
452 pkt->isWrite() ? "write" : "read", pkt->getAddr());
453 }
454
455 if (access_phys_mem) {
456 // The attached physmem contains the official version of data.
457 // The following command performs the real functional access.
458 // This line should be removed once Ruby supplies the official version
459 // of data.
460 ruby_port->system->getPhysMem().functionalAccess(pkt);
461 }
462
463 // turn packet around to go back to requester if response expected
464 if (needsResponse) {
465 pkt->setFunctionalResponseStatus(accessSucceeded);
466
467 // @todo There should not be a reverse call since the response is
468 // communicated through the packet pointer
469 // DPRINTF(RubyPort, "Sending packet back over port\n");
470 // sendFunctional(pkt);
471 }
472 DPRINTF(RubyPort, "Functional access %s!\n",
473 accessSucceeded ? "successful":"failed");
474}
475
476void
477RubyPort::ruby_hit_callback(PacketPtr pkt)
478{
479 // Retrieve the request port from the sender State
480 RubyPort::SenderState *senderState =
481 safe_cast<RubyPort::SenderState *>(pkt->senderState);
482 M5Port *port = senderState->port;
483 assert(port != NULL);
484
485 // pop the sender state from the packet
486 pkt->senderState = senderState->saved;
487 delete senderState;
488
489 port->hitCallback(pkt);
490
491 //
492 // If we had to stall the M5Ports, wake them up because the sequencer
493 // likely has free resources now.
494 //
495 if (waitingOnSequencer) {
496 //
497 // Record the current list of ports to retry on a temporary list before
498 // calling sendRetry on those ports. sendRetry will cause an
499 // immediate retry, which may result in the ports being put back on the
500 // list. Therefore we want to clear the retryList before calling
501 // sendRetry.
502 //
503 std::list<M5Port*> curRetryList(retryList);
504
505 retryList.clear();
506 waitingOnSequencer = false;
507
508 for (std::list<M5Port*>::iterator i = curRetryList.begin();
509 i != curRetryList.end(); ++i) {
510 DPRINTF(RubyPort,
511 "Sequencer may now be free. SendRetry to port %s\n",
512 (*i)->name());
513 (*i)->onRetryList(false);
514 (*i)->sendRetry();
515 }
516 }
517
518 testDrainComplete();
519}
520
521void
522RubyPort::testDrainComplete()
523{
524 //If we weren't able to drain before, we might be able to now.
525 if (drainEvent != NULL) {
526 unsigned int drainCount = getDrainCount(drainEvent);
527 DPRINTF(Config, "Drain count: %u\n", drainCount);
528 if (drainCount == 0) {
529 drainEvent->process();
530 // Clear the drain event once we're done with it.
531 drainEvent = NULL;
532 }
533 }
534}
535
536unsigned int
537RubyPort::getDrainCount(Event *de)
538{
539 int count = 0;
540 //
541 // If the sequencer is not empty, then requests need to drain.
542 // The outstandingCount is the number of requests outstanding and thus the
543 // number of times M5's timing port will process the drain event.
544 //
545 count += outstandingCount();
546
547 DPRINTF(Config, "outstanding count %d\n", outstandingCount());
548
549 // To simplify the draining process, the sequencer's deadlock detection
550 // event should have been descheduled.
551 assert(isDeadlockEventScheduled() == false);
552
553 if (pio_port.isConnected()) {
554 count += pio_port.drain(de);
555 DPRINTF(Config, "count after pio check %d\n", count);
556 }
557
558 for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) {
559 count += (*p)->drain(de);
560 DPRINTF(Config, "count after slave port check %d\n", count);
561 }
562
563 for (std::vector<PioPort*>::iterator p = master_ports.begin();
564 p != master_ports.end(); ++p) {
565 count += (*p)->drain(de);
566 DPRINTF(Config, "count after master port check %d\n", count);
567 }
568
569 DPRINTF(Config, "final count %d\n", count);
570
571 return count;
572}
573
574unsigned int
575RubyPort::drain(Event *de)
576{
577 if (isDeadlockEventScheduled()) {
578 descheduleDeadlockEvent();
579 }
580
581 int count = getDrainCount(de);
582
583 // Set status
584 if (count != 0) {
585 drainEvent = de;
586
587 changeState(SimObject::Draining);
588 return count;
589 }
590
591 changeState(SimObject::Drained);
592 return 0;
593}
594
595void
596RubyPort::M5Port::hitCallback(PacketPtr pkt)
597{
598 bool needsResponse = pkt->needsResponse();
599
600 //
601 // Unless specified at configuraiton, all responses except failed SC
602 // and Flush operations access M5 physical memory.
603 //
604 bool accessPhysMem = access_phys_mem;
605
606 if (pkt->isLLSC()) {
607 if (pkt->isWrite()) {
608 if (pkt->req->getExtraData() != 0) {
609 //
610 // Successful SC packets convert to normal writes
611 //
612 pkt->convertScToWrite();
613 } else {
614 //
615 // Failed SC packets don't access physical memory and thus
616 // the RubyPort itself must convert it to a response.
617 //
618 accessPhysMem = false;
619 }
620 } else {
621 //
622 // All LL packets convert to normal loads so that M5 PhysMem does
623 // not lock the blocks.
624 //
625 pkt->convertLlToRead();
626 }
627 }
628
629 //
630 // Flush requests don't access physical memory
631 //
632 if (pkt->isFlush()) {
633 accessPhysMem = false;
634 }
635
636 DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse);
637
638 if (accessPhysMem) {
639 ruby_port->system->getPhysMem().access(pkt);
640 } else if (needsResponse) {
641 pkt->makeResponse();
642 }
643
644 // turn packet around to go back to requester if response expected
645 if (needsResponse) {
646 DPRINTF(RubyPort, "Sending packet back over port\n");
647 sendNextCycle(pkt);
648 } else {
649 delete pkt;
650 }
651 DPRINTF(RubyPort, "Hit callback done!\n");
652}
653
654bool
655RubyPort::M5Port::sendNextCycle(PacketPtr pkt, bool send_as_snoop)
656{
657 //minimum latency, must be > 0
658 queue.schedSendTiming(pkt, curTick() + (1 * g_eventQueue_ptr->getClock()),
659 send_as_snoop);
660 return true;
661}
662
663bool
664RubyPort::PioPort::sendNextCycle(PacketPtr pkt)
665{
666 //minimum latency, must be > 0
667 queue.schedSendTiming(pkt, curTick() + (1 * g_eventQueue_ptr->getClock()));
668 return true;
669}
670
671AddrRangeList
672RubyPort::M5Port::getAddrRanges()
673{
674 // at the moment the assumption is that the master does not care
675 AddrRangeList ranges;
676 return ranges;
677}
678
679bool
680RubyPort::M5Port::isPhysMemAddress(Addr addr)
681{
682 return ruby_port->system->isMemAddr(addr);
683}
684
685unsigned
686RubyPort::M5Port::deviceBlockSize() const
687{
688 return (unsigned) RubySystem::getBlockSizeBytes();
689}
690
691void
692RubyPort::ruby_eviction_callback(const Address& address)
693{
694 DPRINTF(RubyPort, "Sending invalidations.\n");
695 // should this really be using funcMasterId?
696 Request req(address.getAddress(), 0, 0, Request::funcMasterId);
697 for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) {
|