1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009-2013 Advanced Micro Devices, Inc.
15 * Copyright (c) 2011 Mark D. Hill and David A. Wood
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
42#include "mem/ruby/system/RubyPort.hh"
43
44#include "cpu/testers/rubytest/RubyTester.hh"
45#include "debug/Config.hh"
46#include "debug/Drain.hh"
47#include "debug/Ruby.hh"
48#include "mem/protocol/AccessPermission.hh"
49#include "mem/ruby/slicc_interface/AbstractController.hh"
50#include "mem/simple_mem.hh"
51#include "sim/full_system.hh"
52#include "sim/system.hh"
53
54RubyPort::RubyPort(const Params *p)
| 1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009-2013 Advanced Micro Devices, Inc.
15 * Copyright (c) 2011 Mark D. Hill and David A. Wood
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
42#include "mem/ruby/system/RubyPort.hh"
43
44#include "cpu/testers/rubytest/RubyTester.hh"
45#include "debug/Config.hh"
46#include "debug/Drain.hh"
47#include "debug/Ruby.hh"
48#include "mem/protocol/AccessPermission.hh"
49#include "mem/ruby/slicc_interface/AbstractController.hh"
50#include "mem/simple_mem.hh"
51#include "sim/full_system.hh"
52#include "sim/system.hh"
53
54RubyPort::RubyPort(const Params *p)
|
56 m_controller(NULL), m_mandatory_q_ptr(NULL),
57 m_usingRubyTester(p->using_ruby_tester), system(p->system),
58 pioMasterPort(csprintf("%s.pio-master-port", name()), this),
59 pioSlavePort(csprintf("%s.pio-slave-port", name()), this),
60 memMasterPort(csprintf("%s.mem-master-port", name()), this),
61 memSlavePort(csprintf("%s-mem-slave-port", name()), this,
62 p->ruby_system->getAccessBackingStore(), -1,
63 p->no_retry_on_stall),
64 gotAddrRanges(p->port_master_connection_count),
65 m_isCPUSequencer(p->is_cpu_sequencer)
66{
67 assert(m_version != -1);
68
69 // create the slave ports based on the number of connected ports
70 for (size_t i = 0; i < p->port_slave_connection_count; ++i) {
71 slave_ports.push_back(new MemSlavePort(csprintf("%s.slave%d", name(),
72 i), this, p->ruby_system->getAccessBackingStore(),
73 i, p->no_retry_on_stall));
74 }
75
76 // create the master ports based on the number of connected ports
77 for (size_t i = 0; i < p->port_master_connection_count; ++i) {
78 master_ports.push_back(new PioMasterPort(csprintf("%s.master%d",
79 name(), i), this));
80 }
81}
82
83void
84RubyPort::init()
85{
86 assert(m_controller != NULL);
87 m_mandatory_q_ptr = m_controller->getMandatoryQueue();
88}
89
90Port &
91RubyPort::getPort(const std::string &if_name, PortID idx)
92{
93 if (if_name == "mem_master_port") {
94 return memMasterPort;
95 } else if (if_name == "pio_master_port") {
96 return pioMasterPort;
97 } else if (if_name == "mem_slave_port") {
98 return memSlavePort;
99 } else if (if_name == "pio_slave_port") {
100 return pioSlavePort;
101 } else if (if_name == "master") {
102 // used by the x86 CPUs to connect the interrupt PIO and interrupt
103 // slave port
104 if (idx >= static_cast<PortID>(master_ports.size())) {
105 panic("RubyPort::getPort master: unknown index %d\n", idx);
106 }
107
108 return *master_ports[idx];
109 } else if (if_name == "slave") {
110 // used by the CPUs to connect the caches to the interconnect, and
111 // for the x86 case also the interrupt master
112 if (idx >= static_cast<PortID>(slave_ports.size())) {
113 panic("RubyPort::getPort slave: unknown index %d\n", idx);
114 }
115
116 return *slave_ports[idx];
117 }
118
119 // pass it along to our super class
| 56 m_controller(NULL), m_mandatory_q_ptr(NULL),
57 m_usingRubyTester(p->using_ruby_tester), system(p->system),
58 pioMasterPort(csprintf("%s.pio-master-port", name()), this),
59 pioSlavePort(csprintf("%s.pio-slave-port", name()), this),
60 memMasterPort(csprintf("%s.mem-master-port", name()), this),
61 memSlavePort(csprintf("%s-mem-slave-port", name()), this,
62 p->ruby_system->getAccessBackingStore(), -1,
63 p->no_retry_on_stall),
64 gotAddrRanges(p->port_master_connection_count),
65 m_isCPUSequencer(p->is_cpu_sequencer)
66{
67 assert(m_version != -1);
68
69 // create the slave ports based on the number of connected ports
70 for (size_t i = 0; i < p->port_slave_connection_count; ++i) {
71 slave_ports.push_back(new MemSlavePort(csprintf("%s.slave%d", name(),
72 i), this, p->ruby_system->getAccessBackingStore(),
73 i, p->no_retry_on_stall));
74 }
75
76 // create the master ports based on the number of connected ports
77 for (size_t i = 0; i < p->port_master_connection_count; ++i) {
78 master_ports.push_back(new PioMasterPort(csprintf("%s.master%d",
79 name(), i), this));
80 }
81}
82
83void
84RubyPort::init()
85{
86 assert(m_controller != NULL);
87 m_mandatory_q_ptr = m_controller->getMandatoryQueue();
88}
89
90Port &
91RubyPort::getPort(const std::string &if_name, PortID idx)
92{
93 if (if_name == "mem_master_port") {
94 return memMasterPort;
95 } else if (if_name == "pio_master_port") {
96 return pioMasterPort;
97 } else if (if_name == "mem_slave_port") {
98 return memSlavePort;
99 } else if (if_name == "pio_slave_port") {
100 return pioSlavePort;
101 } else if (if_name == "master") {
102 // used by the x86 CPUs to connect the interrupt PIO and interrupt
103 // slave port
104 if (idx >= static_cast<PortID>(master_ports.size())) {
105 panic("RubyPort::getPort master: unknown index %d\n", idx);
106 }
107
108 return *master_ports[idx];
109 } else if (if_name == "slave") {
110 // used by the CPUs to connect the caches to the interconnect, and
111 // for the x86 case also the interrupt master
112 if (idx >= static_cast<PortID>(slave_ports.size())) {
113 panic("RubyPort::getPort slave: unknown index %d\n", idx);
114 }
115
116 return *slave_ports[idx];
117 }
118
119 // pass it along to our super class
|
121}
122
123RubyPort::PioMasterPort::PioMasterPort(const std::string &_name,
124 RubyPort *_port)
125 : QueuedMasterPort(_name, _port, reqQueue, snoopRespQueue),
126 reqQueue(*_port, *this), snoopRespQueue(*_port, *this)
127{
128 DPRINTF(RubyPort, "Created master pioport on sequencer %s\n", _name);
129}
130
131RubyPort::PioSlavePort::PioSlavePort(const std::string &_name,
132 RubyPort *_port)
133 : QueuedSlavePort(_name, _port, queue), queue(*_port, *this)
134{
135 DPRINTF(RubyPort, "Created slave pioport on sequencer %s\n", _name);
136}
137
138RubyPort::MemMasterPort::MemMasterPort(const std::string &_name,
139 RubyPort *_port)
140 : QueuedMasterPort(_name, _port, reqQueue, snoopRespQueue),
141 reqQueue(*_port, *this), snoopRespQueue(*_port, *this)
142{
143 DPRINTF(RubyPort, "Created master memport on ruby sequencer %s\n", _name);
144}
145
146RubyPort::MemSlavePort::MemSlavePort(const std::string &_name, RubyPort *_port,
147 bool _access_backing_store, PortID id,
148 bool _no_retry_on_stall)
149 : QueuedSlavePort(_name, _port, queue, id), queue(*_port, *this),
150 access_backing_store(_access_backing_store),
151 no_retry_on_stall(_no_retry_on_stall)
152{
153 DPRINTF(RubyPort, "Created slave memport on ruby sequencer %s\n", _name);
154}
155
156bool
157RubyPort::PioMasterPort::recvTimingResp(PacketPtr pkt)
158{
159 RubyPort *rp = static_cast<RubyPort *>(&owner);
160 DPRINTF(RubyPort, "Response for address: 0x%#x\n", pkt->getAddr());
161
162 // send next cycle
163 rp->pioSlavePort.schedTimingResp(
164 pkt, curTick() + rp->m_ruby_system->clockPeriod());
165 return true;
166}
167
168bool RubyPort::MemMasterPort::recvTimingResp(PacketPtr pkt)
169{
170 // got a response from a device
171 assert(pkt->isResponse());
172
173 // First we must retrieve the request port from the sender State
174 RubyPort::SenderState *senderState =
175 safe_cast<RubyPort::SenderState *>(pkt->popSenderState());
176 MemSlavePort *port = senderState->port;
177 assert(port != NULL);
178 delete senderState;
179
180 // In FS mode, ruby memory will receive pio responses from devices
181 // and it must forward these responses back to the particular CPU.
182 DPRINTF(RubyPort, "Pio response for address %#x, going to %s\n",
183 pkt->getAddr(), port->name());
184
185 // attempt to send the response in the next cycle
186 RubyPort *rp = static_cast<RubyPort *>(&owner);
187 port->schedTimingResp(pkt, curTick() + rp->m_ruby_system->clockPeriod());
188
189 return true;
190}
191
192bool
193RubyPort::PioSlavePort::recvTimingReq(PacketPtr pkt)
194{
195 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
196
197 for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) {
198 AddrRangeList l = ruby_port->master_ports[i]->getAddrRanges();
199 for (auto it = l.begin(); it != l.end(); ++it) {
200 if (it->contains(pkt->getAddr())) {
201 // generally it is not safe to assume success here as
202 // the port could be blocked
203 bool M5_VAR_USED success =
204 ruby_port->master_ports[i]->sendTimingReq(pkt);
205 assert(success);
206 return true;
207 }
208 }
209 }
210 panic("Should never reach here!\n");
211}
212
213Tick
214RubyPort::PioSlavePort::recvAtomic(PacketPtr pkt)
215{
216 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
217 // Only atomic_noncaching mode supported!
218 if (!ruby_port->system->bypassCaches()) {
219 panic("Ruby supports atomic accesses only in noncaching mode\n");
220 }
221
222 for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) {
223 AddrRangeList l = ruby_port->master_ports[i]->getAddrRanges();
224 for (auto it = l.begin(); it != l.end(); ++it) {
225 if (it->contains(pkt->getAddr())) {
226 return ruby_port->master_ports[i]->sendAtomic(pkt);
227 }
228 }
229 }
230 panic("Could not find address in Ruby PIO address ranges!\n");
231}
232
233bool
234RubyPort::MemSlavePort::recvTimingReq(PacketPtr pkt)
235{
236 DPRINTF(RubyPort, "Timing request for address %#x on port %d\n",
237 pkt->getAddr(), id);
238 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
239
240 if (pkt->cacheResponding())
241 panic("RubyPort should never see request with the "
242 "cacheResponding flag set\n");
243
244 // ruby doesn't support cache maintenance operations at the
245 // moment, as a workaround, we respond right away
246 if (pkt->req->isCacheMaintenance()) {
247 warn_once("Cache maintenance operations are not supported in Ruby.\n");
248 pkt->makeResponse();
249 schedTimingResp(pkt, curTick());
250 return true;
251 }
252 // Check for pio requests and directly send them to the dedicated
253 // pio port.
254 if (pkt->cmd != MemCmd::MemFenceReq) {
255 if (!isPhysMemAddress(pkt->getAddr())) {
256 assert(ruby_port->memMasterPort.isConnected());
257 DPRINTF(RubyPort, "Request address %#x assumed to be a "
258 "pio address\n", pkt->getAddr());
259
260 // Save the port in the sender state object to be used later to
261 // route the response
262 pkt->pushSenderState(new SenderState(this));
263
264 // send next cycle
265 RubySystem *rs = ruby_port->m_ruby_system;
266 ruby_port->memMasterPort.schedTimingReq(pkt,
267 curTick() + rs->clockPeriod());
268 return true;
269 }
270
271 assert(getOffset(pkt->getAddr()) + pkt->getSize() <=
272 RubySystem::getBlockSizeBytes());
273 }
274
275 // Submit the ruby request
276 RequestStatus requestStatus = ruby_port->makeRequest(pkt);
277
278 // If the request successfully issued then we should return true.
279 // Otherwise, we need to tell the port to retry at a later point
280 // and return false.
281 if (requestStatus == RequestStatus_Issued) {
282 // Save the port in the sender state object to be used later to
283 // route the response
284 pkt->pushSenderState(new SenderState(this));
285
286 DPRINTF(RubyPort, "Request %s address %#x issued\n", pkt->cmdString(),
287 pkt->getAddr());
288 return true;
289 }
290
291 if (pkt->cmd != MemCmd::MemFenceReq) {
292 DPRINTF(RubyPort,
293 "Request %s for address %#x did not issue because %s\n",
294 pkt->cmdString(), pkt->getAddr(),
295 RequestStatus_to_string(requestStatus));
296 }
297
298 addToRetryList();
299
300 return false;
301}
302
303Tick
304RubyPort::MemSlavePort::recvAtomic(PacketPtr pkt)
305{
306 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
307 // Only atomic_noncaching mode supported!
308 if (!ruby_port->system->bypassCaches()) {
309 panic("Ruby supports atomic accesses only in noncaching mode\n");
310 }
311
312 // Check for pio requests and directly send them to the dedicated
313 // pio port.
314 if (pkt->cmd != MemCmd::MemFenceReq) {
315 if (!isPhysMemAddress(pkt->getAddr())) {
316 assert(ruby_port->memMasterPort.isConnected());
317 DPRINTF(RubyPort, "Request address %#x assumed to be a "
318 "pio address\n", pkt->getAddr());
319
320 // Save the port in the sender state object to be used later to
321 // route the response
322 pkt->pushSenderState(new SenderState(this));
323
324 // send next cycle
325 Tick req_ticks = ruby_port->memMasterPort.sendAtomic(pkt);
326 return ruby_port->ticksToCycles(req_ticks);
327 }
328
329 assert(getOffset(pkt->getAddr()) + pkt->getSize() <=
330 RubySystem::getBlockSizeBytes());
331 }
332
333 // Find appropriate directory for address
334 // This assumes that protocols have a Directory machine,
335 // which has its memPort hooked up to memory. This can
336 // fail for some custom protocols.
337 MachineID id = ruby_port->m_controller->mapAddressToMachine(
338 pkt->getAddr(), MachineType_Directory);
339 RubySystem *rs = ruby_port->m_ruby_system;
340 AbstractController *directory =
341 rs->m_abstract_controls[id.getType()][id.getNum()];
342 return directory->recvAtomic(pkt);
343}
344
345void
346RubyPort::MemSlavePort::addToRetryList()
347{
348 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
349
350 //
351 // Unless the requestor do not want retries (e.g., the Ruby tester),
352 // record the stalled M5 port for later retry when the sequencer
353 // becomes free.
354 //
355 if (!no_retry_on_stall && !ruby_port->onRetryList(this)) {
356 ruby_port->addToRetryList(this);
357 }
358}
359
360void
361RubyPort::MemSlavePort::recvFunctional(PacketPtr pkt)
362{
363 DPRINTF(RubyPort, "Functional access for address: %#x\n", pkt->getAddr());
364
365 RubyPort *rp M5_VAR_USED = static_cast<RubyPort *>(&owner);
366 RubySystem *rs = rp->m_ruby_system;
367
368 // Check for pio requests and directly send them to the dedicated
369 // pio port.
370 if (!isPhysMemAddress(pkt->getAddr())) {
371 DPRINTF(RubyPort, "Pio Request for address: 0x%#x\n", pkt->getAddr());
372 assert(rp->pioMasterPort.isConnected());
373 rp->pioMasterPort.sendFunctional(pkt);
374 return;
375 }
376
377 assert(pkt->getAddr() + pkt->getSize() <=
378 makeLineAddress(pkt->getAddr()) + RubySystem::getBlockSizeBytes());
379
380 if (access_backing_store) {
381 // The attached physmem contains the official version of data.
382 // The following command performs the real functional access.
383 // This line should be removed once Ruby supplies the official version
384 // of data.
385 rs->getPhysMem()->functionalAccess(pkt);
386 } else {
387 bool accessSucceeded = false;
388 bool needsResponse = pkt->needsResponse();
389
390 // Do the functional access on ruby memory
391 if (pkt->isRead()) {
392 accessSucceeded = rs->functionalRead(pkt);
393 } else if (pkt->isWrite()) {
394 accessSucceeded = rs->functionalWrite(pkt);
395 } else {
396 panic("Unsupported functional command %s\n", pkt->cmdString());
397 }
398
399 // Unless the requester explicitly said otherwise, generate an error if
400 // the functional request failed
401 if (!accessSucceeded && !pkt->suppressFuncError()) {
402 fatal("Ruby functional %s failed for address %#x\n",
403 pkt->isWrite() ? "write" : "read", pkt->getAddr());
404 }
405
406 // turn packet around to go back to requester if response expected
407 if (needsResponse) {
408 pkt->setFunctionalResponseStatus(accessSucceeded);
409 }
410
411 DPRINTF(RubyPort, "Functional access %s!\n",
412 accessSucceeded ? "successful":"failed");
413 }
414}
415
416void
417RubyPort::ruby_hit_callback(PacketPtr pkt)
418{
419 DPRINTF(RubyPort, "Hit callback for %s 0x%x\n", pkt->cmdString(),
420 pkt->getAddr());
421
422 // The packet was destined for memory and has not yet been turned
423 // into a response
424 assert(system->isMemAddr(pkt->getAddr()));
425 assert(pkt->isRequest());
426
427 // First we must retrieve the request port from the sender State
428 RubyPort::SenderState *senderState =
429 safe_cast<RubyPort::SenderState *>(pkt->popSenderState());
430 MemSlavePort *port = senderState->port;
431 assert(port != NULL);
432 delete senderState;
433
434 port->hitCallback(pkt);
435
436 trySendRetries();
437}
438
439void
440RubyPort::trySendRetries()
441{
442 //
443 // If we had to stall the MemSlavePorts, wake them up because the sequencer
444 // likely has free resources now.
445 //
446 if (!retryList.empty()) {
447 // Record the current list of ports to retry on a temporary list
448 // before calling sendRetryReq on those ports. sendRetryReq will cause
449 // an immediate retry, which may result in the ports being put back on
450 // the list. Therefore we want to clear the retryList before calling
451 // sendRetryReq.
452 std::vector<MemSlavePort *> curRetryList(retryList);
453
454 retryList.clear();
455
456 for (auto i = curRetryList.begin(); i != curRetryList.end(); ++i) {
457 DPRINTF(RubyPort,
458 "Sequencer may now be free. SendRetry to port %s\n",
459 (*i)->name());
460 (*i)->sendRetryReq();
461 }
462 }
463}
464
465void
466RubyPort::testDrainComplete()
467{
468 //If we weren't able to drain before, we might be able to now.
469 if (drainState() == DrainState::Draining) {
470 unsigned int drainCount = outstandingCount();
471 DPRINTF(Drain, "Drain count: %u\n", drainCount);
472 if (drainCount == 0) {
473 DPRINTF(Drain, "RubyPort done draining, signaling drain done\n");
474 signalDrainDone();
475 }
476 }
477}
478
479DrainState
480RubyPort::drain()
481{
482 if (isDeadlockEventScheduled()) {
483 descheduleDeadlockEvent();
484 }
485
486 //
487 // If the RubyPort is not empty, then it needs to clear all outstanding
488 // requests before it should call signalDrainDone()
489 //
490 DPRINTF(Config, "outstanding count %d\n", outstandingCount());
491 if (outstandingCount() > 0) {
492 DPRINTF(Drain, "RubyPort not drained\n");
493 return DrainState::Draining;
494 } else {
495 return DrainState::Drained;
496 }
497}
498
499void
500RubyPort::MemSlavePort::hitCallback(PacketPtr pkt)
501{
502 bool needsResponse = pkt->needsResponse();
503
504 // Unless specified at configuraiton, all responses except failed SC
505 // and Flush operations access M5 physical memory.
506 bool accessPhysMem = access_backing_store;
507
508 if (pkt->isLLSC()) {
509 if (pkt->isWrite()) {
510 if (pkt->req->getExtraData() != 0) {
511 //
512 // Successful SC packets convert to normal writes
513 //
514 pkt->convertScToWrite();
515 } else {
516 //
517 // Failed SC packets don't access physical memory and thus
518 // the RubyPort itself must convert it to a response.
519 //
520 accessPhysMem = false;
521 }
522 } else {
523 //
524 // All LL packets convert to normal loads so that M5 PhysMem does
525 // not lock the blocks.
526 //
527 pkt->convertLlToRead();
528 }
529 }
530
531 // Flush, acquire, release requests don't access physical memory
532 if (pkt->isFlush() || pkt->cmd == MemCmd::MemFenceReq) {
533 accessPhysMem = false;
534 }
535
536 if (pkt->req->isKernel()) {
537 accessPhysMem = false;
538 needsResponse = true;
539 }
540
541 DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse);
542
543 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
544 RubySystem *rs = ruby_port->m_ruby_system;
545 if (accessPhysMem) {
546 rs->getPhysMem()->access(pkt);
547 } else if (needsResponse) {
548 pkt->makeResponse();
549 }
550
551 // turn packet around to go back to requester if response expected
552 if (needsResponse) {
553 DPRINTF(RubyPort, "Sending packet back over port\n");
554 // Send a response in the same cycle. There is no need to delay the
555 // response because the response latency is already incurred in the
556 // Ruby protocol.
557 schedTimingResp(pkt, curTick());
558 } else {
559 delete pkt;
560 }
561
562 DPRINTF(RubyPort, "Hit callback done!\n");
563}
564
565AddrRangeList
566RubyPort::PioSlavePort::getAddrRanges() const
567{
568 // at the moment the assumption is that the master does not care
569 AddrRangeList ranges;
570 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
571
572 for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) {
573 ranges.splice(ranges.begin(),
574 ruby_port->master_ports[i]->getAddrRanges());
575 }
576 for (const auto M5_VAR_USED &r : ranges)
577 DPRINTF(RubyPort, "%s\n", r.to_string());
578 return ranges;
579}
580
581bool
582RubyPort::MemSlavePort::isPhysMemAddress(Addr addr) const
583{
584 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
585 return ruby_port->system->isMemAddr(addr);
586}
587
588void
589RubyPort::ruby_eviction_callback(Addr address)
590{
591 DPRINTF(RubyPort, "Sending invalidations.\n");
592 // Allocate the invalidate request and packet on the stack, as it is
593 // assumed they will not be modified or deleted by receivers.
594 // TODO: should this really be using funcMasterId?
595 auto request = std::make_shared<Request>(
596 address, RubySystem::getBlockSizeBytes(), 0,
597 Request::funcMasterId);
598
599 // Use a single packet to signal all snooping ports of the invalidation.
600 // This assumes that snooping ports do NOT modify the packet/request
601 Packet pkt(request, MemCmd::InvalidateReq);
602 for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) {
603 // check if the connected master port is snooping
604 if ((*p)->isSnooping()) {
605 // send as a snoop request
606 (*p)->sendTimingSnoopReq(&pkt);
607 }
608 }
609}
610
611void
612RubyPort::PioMasterPort::recvRangeChange()
613{
614 RubyPort &r = static_cast<RubyPort &>(owner);
615 r.gotAddrRanges--;
616 if (r.gotAddrRanges == 0 && FullSystem) {
617 r.pioSlavePort.sendRangeChange();
618 }
619}
| 121}
122
123RubyPort::PioMasterPort::PioMasterPort(const std::string &_name,
124 RubyPort *_port)
125 : QueuedMasterPort(_name, _port, reqQueue, snoopRespQueue),
126 reqQueue(*_port, *this), snoopRespQueue(*_port, *this)
127{
128 DPRINTF(RubyPort, "Created master pioport on sequencer %s\n", _name);
129}
130
131RubyPort::PioSlavePort::PioSlavePort(const std::string &_name,
132 RubyPort *_port)
133 : QueuedSlavePort(_name, _port, queue), queue(*_port, *this)
134{
135 DPRINTF(RubyPort, "Created slave pioport on sequencer %s\n", _name);
136}
137
138RubyPort::MemMasterPort::MemMasterPort(const std::string &_name,
139 RubyPort *_port)
140 : QueuedMasterPort(_name, _port, reqQueue, snoopRespQueue),
141 reqQueue(*_port, *this), snoopRespQueue(*_port, *this)
142{
143 DPRINTF(RubyPort, "Created master memport on ruby sequencer %s\n", _name);
144}
145
146RubyPort::MemSlavePort::MemSlavePort(const std::string &_name, RubyPort *_port,
147 bool _access_backing_store, PortID id,
148 bool _no_retry_on_stall)
149 : QueuedSlavePort(_name, _port, queue, id), queue(*_port, *this),
150 access_backing_store(_access_backing_store),
151 no_retry_on_stall(_no_retry_on_stall)
152{
153 DPRINTF(RubyPort, "Created slave memport on ruby sequencer %s\n", _name);
154}
155
156bool
157RubyPort::PioMasterPort::recvTimingResp(PacketPtr pkt)
158{
159 RubyPort *rp = static_cast<RubyPort *>(&owner);
160 DPRINTF(RubyPort, "Response for address: 0x%#x\n", pkt->getAddr());
161
162 // send next cycle
163 rp->pioSlavePort.schedTimingResp(
164 pkt, curTick() + rp->m_ruby_system->clockPeriod());
165 return true;
166}
167
168bool RubyPort::MemMasterPort::recvTimingResp(PacketPtr pkt)
169{
170 // got a response from a device
171 assert(pkt->isResponse());
172
173 // First we must retrieve the request port from the sender State
174 RubyPort::SenderState *senderState =
175 safe_cast<RubyPort::SenderState *>(pkt->popSenderState());
176 MemSlavePort *port = senderState->port;
177 assert(port != NULL);
178 delete senderState;
179
180 // In FS mode, ruby memory will receive pio responses from devices
181 // and it must forward these responses back to the particular CPU.
182 DPRINTF(RubyPort, "Pio response for address %#x, going to %s\n",
183 pkt->getAddr(), port->name());
184
185 // attempt to send the response in the next cycle
186 RubyPort *rp = static_cast<RubyPort *>(&owner);
187 port->schedTimingResp(pkt, curTick() + rp->m_ruby_system->clockPeriod());
188
189 return true;
190}
191
192bool
193RubyPort::PioSlavePort::recvTimingReq(PacketPtr pkt)
194{
195 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
196
197 for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) {
198 AddrRangeList l = ruby_port->master_ports[i]->getAddrRanges();
199 for (auto it = l.begin(); it != l.end(); ++it) {
200 if (it->contains(pkt->getAddr())) {
201 // generally it is not safe to assume success here as
202 // the port could be blocked
203 bool M5_VAR_USED success =
204 ruby_port->master_ports[i]->sendTimingReq(pkt);
205 assert(success);
206 return true;
207 }
208 }
209 }
210 panic("Should never reach here!\n");
211}
212
213Tick
214RubyPort::PioSlavePort::recvAtomic(PacketPtr pkt)
215{
216 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
217 // Only atomic_noncaching mode supported!
218 if (!ruby_port->system->bypassCaches()) {
219 panic("Ruby supports atomic accesses only in noncaching mode\n");
220 }
221
222 for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) {
223 AddrRangeList l = ruby_port->master_ports[i]->getAddrRanges();
224 for (auto it = l.begin(); it != l.end(); ++it) {
225 if (it->contains(pkt->getAddr())) {
226 return ruby_port->master_ports[i]->sendAtomic(pkt);
227 }
228 }
229 }
230 panic("Could not find address in Ruby PIO address ranges!\n");
231}
232
233bool
234RubyPort::MemSlavePort::recvTimingReq(PacketPtr pkt)
235{
236 DPRINTF(RubyPort, "Timing request for address %#x on port %d\n",
237 pkt->getAddr(), id);
238 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
239
240 if (pkt->cacheResponding())
241 panic("RubyPort should never see request with the "
242 "cacheResponding flag set\n");
243
244 // ruby doesn't support cache maintenance operations at the
245 // moment, as a workaround, we respond right away
246 if (pkt->req->isCacheMaintenance()) {
247 warn_once("Cache maintenance operations are not supported in Ruby.\n");
248 pkt->makeResponse();
249 schedTimingResp(pkt, curTick());
250 return true;
251 }
252 // Check for pio requests and directly send them to the dedicated
253 // pio port.
254 if (pkt->cmd != MemCmd::MemFenceReq) {
255 if (!isPhysMemAddress(pkt->getAddr())) {
256 assert(ruby_port->memMasterPort.isConnected());
257 DPRINTF(RubyPort, "Request address %#x assumed to be a "
258 "pio address\n", pkt->getAddr());
259
260 // Save the port in the sender state object to be used later to
261 // route the response
262 pkt->pushSenderState(new SenderState(this));
263
264 // send next cycle
265 RubySystem *rs = ruby_port->m_ruby_system;
266 ruby_port->memMasterPort.schedTimingReq(pkt,
267 curTick() + rs->clockPeriod());
268 return true;
269 }
270
271 assert(getOffset(pkt->getAddr()) + pkt->getSize() <=
272 RubySystem::getBlockSizeBytes());
273 }
274
275 // Submit the ruby request
276 RequestStatus requestStatus = ruby_port->makeRequest(pkt);
277
278 // If the request successfully issued then we should return true.
279 // Otherwise, we need to tell the port to retry at a later point
280 // and return false.
281 if (requestStatus == RequestStatus_Issued) {
282 // Save the port in the sender state object to be used later to
283 // route the response
284 pkt->pushSenderState(new SenderState(this));
285
286 DPRINTF(RubyPort, "Request %s address %#x issued\n", pkt->cmdString(),
287 pkt->getAddr());
288 return true;
289 }
290
291 if (pkt->cmd != MemCmd::MemFenceReq) {
292 DPRINTF(RubyPort,
293 "Request %s for address %#x did not issue because %s\n",
294 pkt->cmdString(), pkt->getAddr(),
295 RequestStatus_to_string(requestStatus));
296 }
297
298 addToRetryList();
299
300 return false;
301}
302
303Tick
304RubyPort::MemSlavePort::recvAtomic(PacketPtr pkt)
305{
306 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
307 // Only atomic_noncaching mode supported!
308 if (!ruby_port->system->bypassCaches()) {
309 panic("Ruby supports atomic accesses only in noncaching mode\n");
310 }
311
312 // Check for pio requests and directly send them to the dedicated
313 // pio port.
314 if (pkt->cmd != MemCmd::MemFenceReq) {
315 if (!isPhysMemAddress(pkt->getAddr())) {
316 assert(ruby_port->memMasterPort.isConnected());
317 DPRINTF(RubyPort, "Request address %#x assumed to be a "
318 "pio address\n", pkt->getAddr());
319
320 // Save the port in the sender state object to be used later to
321 // route the response
322 pkt->pushSenderState(new SenderState(this));
323
324 // send next cycle
325 Tick req_ticks = ruby_port->memMasterPort.sendAtomic(pkt);
326 return ruby_port->ticksToCycles(req_ticks);
327 }
328
329 assert(getOffset(pkt->getAddr()) + pkt->getSize() <=
330 RubySystem::getBlockSizeBytes());
331 }
332
333 // Find appropriate directory for address
334 // This assumes that protocols have a Directory machine,
335 // which has its memPort hooked up to memory. This can
336 // fail for some custom protocols.
337 MachineID id = ruby_port->m_controller->mapAddressToMachine(
338 pkt->getAddr(), MachineType_Directory);
339 RubySystem *rs = ruby_port->m_ruby_system;
340 AbstractController *directory =
341 rs->m_abstract_controls[id.getType()][id.getNum()];
342 return directory->recvAtomic(pkt);
343}
344
345void
346RubyPort::MemSlavePort::addToRetryList()
347{
348 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
349
350 //
351 // Unless the requestor do not want retries (e.g., the Ruby tester),
352 // record the stalled M5 port for later retry when the sequencer
353 // becomes free.
354 //
355 if (!no_retry_on_stall && !ruby_port->onRetryList(this)) {
356 ruby_port->addToRetryList(this);
357 }
358}
359
360void
361RubyPort::MemSlavePort::recvFunctional(PacketPtr pkt)
362{
363 DPRINTF(RubyPort, "Functional access for address: %#x\n", pkt->getAddr());
364
365 RubyPort *rp M5_VAR_USED = static_cast<RubyPort *>(&owner);
366 RubySystem *rs = rp->m_ruby_system;
367
368 // Check for pio requests and directly send them to the dedicated
369 // pio port.
370 if (!isPhysMemAddress(pkt->getAddr())) {
371 DPRINTF(RubyPort, "Pio Request for address: 0x%#x\n", pkt->getAddr());
372 assert(rp->pioMasterPort.isConnected());
373 rp->pioMasterPort.sendFunctional(pkt);
374 return;
375 }
376
377 assert(pkt->getAddr() + pkt->getSize() <=
378 makeLineAddress(pkt->getAddr()) + RubySystem::getBlockSizeBytes());
379
380 if (access_backing_store) {
381 // The attached physmem contains the official version of data.
382 // The following command performs the real functional access.
383 // This line should be removed once Ruby supplies the official version
384 // of data.
385 rs->getPhysMem()->functionalAccess(pkt);
386 } else {
387 bool accessSucceeded = false;
388 bool needsResponse = pkt->needsResponse();
389
390 // Do the functional access on ruby memory
391 if (pkt->isRead()) {
392 accessSucceeded = rs->functionalRead(pkt);
393 } else if (pkt->isWrite()) {
394 accessSucceeded = rs->functionalWrite(pkt);
395 } else {
396 panic("Unsupported functional command %s\n", pkt->cmdString());
397 }
398
399 // Unless the requester explicitly said otherwise, generate an error if
400 // the functional request failed
401 if (!accessSucceeded && !pkt->suppressFuncError()) {
402 fatal("Ruby functional %s failed for address %#x\n",
403 pkt->isWrite() ? "write" : "read", pkt->getAddr());
404 }
405
406 // turn packet around to go back to requester if response expected
407 if (needsResponse) {
408 pkt->setFunctionalResponseStatus(accessSucceeded);
409 }
410
411 DPRINTF(RubyPort, "Functional access %s!\n",
412 accessSucceeded ? "successful":"failed");
413 }
414}
415
416void
417RubyPort::ruby_hit_callback(PacketPtr pkt)
418{
419 DPRINTF(RubyPort, "Hit callback for %s 0x%x\n", pkt->cmdString(),
420 pkt->getAddr());
421
422 // The packet was destined for memory and has not yet been turned
423 // into a response
424 assert(system->isMemAddr(pkt->getAddr()));
425 assert(pkt->isRequest());
426
427 // First we must retrieve the request port from the sender State
428 RubyPort::SenderState *senderState =
429 safe_cast<RubyPort::SenderState *>(pkt->popSenderState());
430 MemSlavePort *port = senderState->port;
431 assert(port != NULL);
432 delete senderState;
433
434 port->hitCallback(pkt);
435
436 trySendRetries();
437}
438
439void
440RubyPort::trySendRetries()
441{
442 //
443 // If we had to stall the MemSlavePorts, wake them up because the sequencer
444 // likely has free resources now.
445 //
446 if (!retryList.empty()) {
447 // Record the current list of ports to retry on a temporary list
448 // before calling sendRetryReq on those ports. sendRetryReq will cause
449 // an immediate retry, which may result in the ports being put back on
450 // the list. Therefore we want to clear the retryList before calling
451 // sendRetryReq.
452 std::vector<MemSlavePort *> curRetryList(retryList);
453
454 retryList.clear();
455
456 for (auto i = curRetryList.begin(); i != curRetryList.end(); ++i) {
457 DPRINTF(RubyPort,
458 "Sequencer may now be free. SendRetry to port %s\n",
459 (*i)->name());
460 (*i)->sendRetryReq();
461 }
462 }
463}
464
465void
466RubyPort::testDrainComplete()
467{
468 //If we weren't able to drain before, we might be able to now.
469 if (drainState() == DrainState::Draining) {
470 unsigned int drainCount = outstandingCount();
471 DPRINTF(Drain, "Drain count: %u\n", drainCount);
472 if (drainCount == 0) {
473 DPRINTF(Drain, "RubyPort done draining, signaling drain done\n");
474 signalDrainDone();
475 }
476 }
477}
478
479DrainState
480RubyPort::drain()
481{
482 if (isDeadlockEventScheduled()) {
483 descheduleDeadlockEvent();
484 }
485
486 //
487 // If the RubyPort is not empty, then it needs to clear all outstanding
488 // requests before it should call signalDrainDone()
489 //
490 DPRINTF(Config, "outstanding count %d\n", outstandingCount());
491 if (outstandingCount() > 0) {
492 DPRINTF(Drain, "RubyPort not drained\n");
493 return DrainState::Draining;
494 } else {
495 return DrainState::Drained;
496 }
497}
498
499void
500RubyPort::MemSlavePort::hitCallback(PacketPtr pkt)
501{
502 bool needsResponse = pkt->needsResponse();
503
504 // Unless specified at configuraiton, all responses except failed SC
505 // and Flush operations access M5 physical memory.
506 bool accessPhysMem = access_backing_store;
507
508 if (pkt->isLLSC()) {
509 if (pkt->isWrite()) {
510 if (pkt->req->getExtraData() != 0) {
511 //
512 // Successful SC packets convert to normal writes
513 //
514 pkt->convertScToWrite();
515 } else {
516 //
517 // Failed SC packets don't access physical memory and thus
518 // the RubyPort itself must convert it to a response.
519 //
520 accessPhysMem = false;
521 }
522 } else {
523 //
524 // All LL packets convert to normal loads so that M5 PhysMem does
525 // not lock the blocks.
526 //
527 pkt->convertLlToRead();
528 }
529 }
530
531 // Flush, acquire, release requests don't access physical memory
532 if (pkt->isFlush() || pkt->cmd == MemCmd::MemFenceReq) {
533 accessPhysMem = false;
534 }
535
536 if (pkt->req->isKernel()) {
537 accessPhysMem = false;
538 needsResponse = true;
539 }
540
541 DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse);
542
543 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
544 RubySystem *rs = ruby_port->m_ruby_system;
545 if (accessPhysMem) {
546 rs->getPhysMem()->access(pkt);
547 } else if (needsResponse) {
548 pkt->makeResponse();
549 }
550
551 // turn packet around to go back to requester if response expected
552 if (needsResponse) {
553 DPRINTF(RubyPort, "Sending packet back over port\n");
554 // Send a response in the same cycle. There is no need to delay the
555 // response because the response latency is already incurred in the
556 // Ruby protocol.
557 schedTimingResp(pkt, curTick());
558 } else {
559 delete pkt;
560 }
561
562 DPRINTF(RubyPort, "Hit callback done!\n");
563}
564
565AddrRangeList
566RubyPort::PioSlavePort::getAddrRanges() const
567{
568 // at the moment the assumption is that the master does not care
569 AddrRangeList ranges;
570 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
571
572 for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) {
573 ranges.splice(ranges.begin(),
574 ruby_port->master_ports[i]->getAddrRanges());
575 }
576 for (const auto M5_VAR_USED &r : ranges)
577 DPRINTF(RubyPort, "%s\n", r.to_string());
578 return ranges;
579}
580
581bool
582RubyPort::MemSlavePort::isPhysMemAddress(Addr addr) const
583{
584 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
585 return ruby_port->system->isMemAddr(addr);
586}
587
588void
589RubyPort::ruby_eviction_callback(Addr address)
590{
591 DPRINTF(RubyPort, "Sending invalidations.\n");
592 // Allocate the invalidate request and packet on the stack, as it is
593 // assumed they will not be modified or deleted by receivers.
594 // TODO: should this really be using funcMasterId?
595 auto request = std::make_shared<Request>(
596 address, RubySystem::getBlockSizeBytes(), 0,
597 Request::funcMasterId);
598
599 // Use a single packet to signal all snooping ports of the invalidation.
600 // This assumes that snooping ports do NOT modify the packet/request
601 Packet pkt(request, MemCmd::InvalidateReq);
602 for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) {
603 // check if the connected master port is snooping
604 if ((*p)->isSnooping()) {
605 // send as a snoop request
606 (*p)->sendTimingSnoopReq(&pkt);
607 }
608 }
609}
610
611void
612RubyPort::PioMasterPort::recvRangeChange()
613{
614 RubyPort &r = static_cast<RubyPort &>(owner);
615 r.gotAddrRanges--;
616 if (r.gotAddrRanges == 0 && FullSystem) {
617 r.pioSlavePort.sendRangeChange();
618 }
619}
|