1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009-2013 Advanced Micro Devices, Inc.
15 * Copyright (c) 2011 Mark D. Hill and David A. Wood
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
42#include "mem/ruby/system/RubyPort.hh"
43
44#include "cpu/testers/rubytest/RubyTester.hh"
45#include "debug/Config.hh"
46#include "debug/Drain.hh"
47#include "debug/Ruby.hh"
48#include "mem/protocol/AccessPermission.hh"
49#include "mem/ruby/slicc_interface/AbstractController.hh"
50#include "mem/simple_mem.hh"
51#include "sim/full_system.hh"
52#include "sim/system.hh"
53
54RubyPort::RubyPort(const Params *p)
55 : MemObject(p), m_ruby_system(p->ruby_system), m_version(p->version),
56 m_controller(NULL), m_mandatory_q_ptr(NULL),
57 m_usingRubyTester(p->using_ruby_tester), system(p->system),
58 pioMasterPort(csprintf("%s.pio-master-port", name()), this),
59 pioSlavePort(csprintf("%s.pio-slave-port", name()), this),
60 memMasterPort(csprintf("%s.mem-master-port", name()), this),
61 memSlavePort(csprintf("%s-mem-slave-port", name()), this,
62 p->ruby_system->getAccessBackingStore(), -1,
63 p->no_retry_on_stall),
64 gotAddrRanges(p->port_master_connection_count),
65 m_isCPUSequencer(p->is_cpu_sequencer)
66{
67 assert(m_version != -1);
68
69 // create the slave ports based on the number of connected ports
70 for (size_t i = 0; i < p->port_slave_connection_count; ++i) {
71 slave_ports.push_back(new MemSlavePort(csprintf("%s.slave%d", name(),
72 i), this, p->ruby_system->getAccessBackingStore(),
73 i, p->no_retry_on_stall));
74 }
75
76 // create the master ports based on the number of connected ports
77 for (size_t i = 0; i < p->port_master_connection_count; ++i) {
78 master_ports.push_back(new PioMasterPort(csprintf("%s.master%d",
79 name(), i), this));
80 }
81}
82
83void
84RubyPort::init()
85{
86 assert(m_controller != NULL);
87 m_mandatory_q_ptr = m_controller->getMandatoryQueue();
88}
89
90BaseMasterPort &
91RubyPort::getMasterPort(const std::string &if_name, PortID idx)
92{
93 if (if_name == "mem_master_port") {
94 return memMasterPort;
95 }
96
97 if (if_name == "pio_master_port") {
98 return pioMasterPort;
99 }
100
101 // used by the x86 CPUs to connect the interrupt PIO and interrupt slave
102 // port
103 if (if_name != "master") {
104 // pass it along to our super class
105 return MemObject::getMasterPort(if_name, idx);
106 } else {
107 if (idx >= static_cast<PortID>(master_ports.size())) {
108 panic("RubyPort::getMasterPort: unknown index %d\n", idx);
109 }
110
111 return *master_ports[idx];
112 }
113}
114
115BaseSlavePort &
116RubyPort::getSlavePort(const std::string &if_name, PortID idx)
117{
118 if (if_name == "mem_slave_port") {
119 return memSlavePort;
120 }
121
122 if (if_name == "pio_slave_port")
123 return pioSlavePort;
124
125 // used by the CPUs to connect the caches to the interconnect, and
126 // for the x86 case also the interrupt master
127 if (if_name != "slave") {
128 // pass it along to our super class
129 return MemObject::getSlavePort(if_name, idx);
130 } else {
131 if (idx >= static_cast<PortID>(slave_ports.size())) {
132 panic("RubyPort::getSlavePort: unknown index %d\n", idx);
133 }
134
135 return *slave_ports[idx];
136 }
137}
138
139RubyPort::PioMasterPort::PioMasterPort(const std::string &_name,
140 RubyPort *_port)
141 : QueuedMasterPort(_name, _port, reqQueue, snoopRespQueue),
142 reqQueue(*_port, *this), snoopRespQueue(*_port, *this)
143{
144 DPRINTF(RubyPort, "Created master pioport on sequencer %s\n", _name);
145}
146
147RubyPort::PioSlavePort::PioSlavePort(const std::string &_name,
148 RubyPort *_port)
149 : QueuedSlavePort(_name, _port, queue), queue(*_port, *this)
150{
151 DPRINTF(RubyPort, "Created slave pioport on sequencer %s\n", _name);
152}
153
154RubyPort::MemMasterPort::MemMasterPort(const std::string &_name,
155 RubyPort *_port)
156 : QueuedMasterPort(_name, _port, reqQueue, snoopRespQueue),
157 reqQueue(*_port, *this), snoopRespQueue(*_port, *this)
158{
159 DPRINTF(RubyPort, "Created master memport on ruby sequencer %s\n", _name);
160}
161
162RubyPort::MemSlavePort::MemSlavePort(const std::string &_name, RubyPort *_port,
163 bool _access_backing_store, PortID id,
164 bool _no_retry_on_stall)
165 : QueuedSlavePort(_name, _port, queue, id), queue(*_port, *this),
166 access_backing_store(_access_backing_store),
167 no_retry_on_stall(_no_retry_on_stall)
168{
169 DPRINTF(RubyPort, "Created slave memport on ruby sequencer %s\n", _name);
170}
171
172bool
173RubyPort::PioMasterPort::recvTimingResp(PacketPtr pkt)
174{
175 RubyPort *rp = static_cast<RubyPort *>(&owner);
176 DPRINTF(RubyPort, "Response for address: 0x%#x\n", pkt->getAddr());
177
178 // send next cycle
179 rp->pioSlavePort.schedTimingResp(
180 pkt, curTick() + rp->m_ruby_system->clockPeriod());
181 return true;
182}
183
184bool RubyPort::MemMasterPort::recvTimingResp(PacketPtr pkt)
185{
186 // got a response from a device
187 assert(pkt->isResponse());
188
189 // First we must retrieve the request port from the sender State
190 RubyPort::SenderState *senderState =
191 safe_cast<RubyPort::SenderState *>(pkt->popSenderState());
192 MemSlavePort *port = senderState->port;
193 assert(port != NULL);
194 delete senderState;
195
196 // In FS mode, ruby memory will receive pio responses from devices
197 // and it must forward these responses back to the particular CPU.
198 DPRINTF(RubyPort, "Pio response for address %#x, going to %s\n",
199 pkt->getAddr(), port->name());
200
201 // attempt to send the response in the next cycle
202 RubyPort *rp = static_cast<RubyPort *>(&owner);
203 port->schedTimingResp(pkt, curTick() + rp->m_ruby_system->clockPeriod());
204
205 return true;
206}
207
208bool
209RubyPort::PioSlavePort::recvTimingReq(PacketPtr pkt)
210{
211 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
212
213 for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) {
214 AddrRangeList l = ruby_port->master_ports[i]->getAddrRanges();
215 for (auto it = l.begin(); it != l.end(); ++it) {
216 if (it->contains(pkt->getAddr())) {
217 // generally it is not safe to assume success here as
218 // the port could be blocked
219 bool M5_VAR_USED success =
220 ruby_port->master_ports[i]->sendTimingReq(pkt);
221 assert(success);
222 return true;
223 }
224 }
225 }
226 panic("Should never reach here!\n");
227}
228
229Tick
230RubyPort::PioSlavePort::recvAtomic(PacketPtr pkt)
231{
232 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
233 // Only atomic_noncaching mode supported!
234 if (!ruby_port->system->bypassCaches()) {
235 panic("Ruby supports atomic accesses only in noncaching mode\n");
236 }
237
238 for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) {
239 AddrRangeList l = ruby_port->master_ports[i]->getAddrRanges();
240 for (auto it = l.begin(); it != l.end(); ++it) {
241 if (it->contains(pkt->getAddr())) {
242 return ruby_port->master_ports[i]->sendAtomic(pkt);
243 }
244 }
245 }
246 panic("Could not find address in Ruby PIO address ranges!\n");
247}
248
249bool
250RubyPort::MemSlavePort::recvTimingReq(PacketPtr pkt)
251{
252 DPRINTF(RubyPort, "Timing request for address %#x on port %d\n",
253 pkt->getAddr(), id);
254 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
255
256 if (pkt->cacheResponding())
257 panic("RubyPort should never see request with the "
258 "cacheResponding flag set\n");
259
260 // ruby doesn't support cache maintenance operations at the
261 // moment, as a workaround, we respond right away
262 if (pkt->req->isCacheMaintenance()) {
263 warn_once("Cache maintenance operations are not supported in Ruby.\n");
264 pkt->makeResponse();
265 schedTimingResp(pkt, curTick());
266 return true;
267 }
268 // Check for pio requests and directly send them to the dedicated
269 // pio port.
270 if (pkt->cmd != MemCmd::MemFenceReq) {
271 if (!isPhysMemAddress(pkt->getAddr())) {
272 assert(ruby_port->memMasterPort.isConnected());
273 DPRINTF(RubyPort, "Request address %#x assumed to be a "
274 "pio address\n", pkt->getAddr());
275
276 // Save the port in the sender state object to be used later to
277 // route the response
278 pkt->pushSenderState(new SenderState(this));
279
280 // send next cycle
281 RubySystem *rs = ruby_port->m_ruby_system;
282 ruby_port->memMasterPort.schedTimingReq(pkt,
283 curTick() + rs->clockPeriod());
284 return true;
285 }
286
287 assert(getOffset(pkt->getAddr()) + pkt->getSize() <=
288 RubySystem::getBlockSizeBytes());
289 }
290
291 // Submit the ruby request
292 RequestStatus requestStatus = ruby_port->makeRequest(pkt);
293
294 // If the request successfully issued then we should return true.
295 // Otherwise, we need to tell the port to retry at a later point
296 // and return false.
297 if (requestStatus == RequestStatus_Issued) {
298 // Save the port in the sender state object to be used later to
299 // route the response
300 pkt->pushSenderState(new SenderState(this));
301
302 DPRINTF(RubyPort, "Request %s address %#x issued\n", pkt->cmdString(),
303 pkt->getAddr());
304 return true;
305 }
306
307 if (pkt->cmd != MemCmd::MemFenceReq) {
308 DPRINTF(RubyPort,
309 "Request %s for address %#x did not issue because %s\n",
310 pkt->cmdString(), pkt->getAddr(),
311 RequestStatus_to_string(requestStatus));
312 }
313
314 addToRetryList();
315
316 return false;
317}
318
319Tick
320RubyPort::MemSlavePort::recvAtomic(PacketPtr pkt)
321{
322 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
323 // Only atomic_noncaching mode supported!
324 if (!ruby_port->system->bypassCaches()) {
325 panic("Ruby supports atomic accesses only in noncaching mode\n");
326 }
327
328 // Check for pio requests and directly send them to the dedicated
329 // pio port.
330 if (pkt->cmd != MemCmd::MemFenceReq) {
331 if (!isPhysMemAddress(pkt->getAddr())) {
332 assert(ruby_port->memMasterPort.isConnected());
333 DPRINTF(RubyPort, "Request address %#x assumed to be a "
334 "pio address\n", pkt->getAddr());
335
336 // Save the port in the sender state object to be used later to
337 // route the response
338 pkt->pushSenderState(new SenderState(this));
339
340 // send next cycle
341 Tick req_ticks = ruby_port->memMasterPort.sendAtomic(pkt);
342 return ruby_port->ticksToCycles(req_ticks);
343 }
344
345 assert(getOffset(pkt->getAddr()) + pkt->getSize() <=
346 RubySystem::getBlockSizeBytes());
347 }
348
349 // Find appropriate directory for address
350 // This assumes that protocols have a Directory machine,
351 // which has its memPort hooked up to memory. This can
352 // fail for some custom protocols.
353 MachineID id = ruby_port->m_controller->mapAddressToMachine(
354 pkt->getAddr(), MachineType_Directory);
355 RubySystem *rs = ruby_port->m_ruby_system;
356 AbstractController *directory =
357 rs->m_abstract_controls[id.getType()][id.getNum()];
358 return directory->recvAtomic(pkt);
359}
360
361void
362RubyPort::MemSlavePort::addToRetryList()
363{
364 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
365
366 //
367 // Unless the requestor do not want retries (e.g., the Ruby tester),
368 // record the stalled M5 port for later retry when the sequencer
369 // becomes free.
370 //
371 if (!no_retry_on_stall && !ruby_port->onRetryList(this)) {
372 ruby_port->addToRetryList(this);
373 }
374}
375
376void
377RubyPort::MemSlavePort::recvFunctional(PacketPtr pkt)
378{
379 DPRINTF(RubyPort, "Functional access for address: %#x\n", pkt->getAddr());
380
381 RubyPort *rp M5_VAR_USED = static_cast<RubyPort *>(&owner);
382 RubySystem *rs = rp->m_ruby_system;
383
384 // Check for pio requests and directly send them to the dedicated
385 // pio port.
386 if (!isPhysMemAddress(pkt->getAddr())) {
387 DPRINTF(RubyPort, "Pio Request for address: 0x%#x\n", pkt->getAddr());
388 assert(rp->pioMasterPort.isConnected());
389 rp->pioMasterPort.sendFunctional(pkt);
390 return;
391 }
392
393 assert(pkt->getAddr() + pkt->getSize() <=
394 makeLineAddress(pkt->getAddr()) + RubySystem::getBlockSizeBytes());
395
396 if (access_backing_store) {
397 // The attached physmem contains the official version of data.
398 // The following command performs the real functional access.
399 // This line should be removed once Ruby supplies the official version
400 // of data.
401 rs->getPhysMem()->functionalAccess(pkt);
402 } else {
403 bool accessSucceeded = false;
404 bool needsResponse = pkt->needsResponse();
405
406 // Do the functional access on ruby memory
407 if (pkt->isRead()) {
408 accessSucceeded = rs->functionalRead(pkt);
409 } else if (pkt->isWrite()) {
410 accessSucceeded = rs->functionalWrite(pkt);
411 } else {
412 panic("Unsupported functional command %s\n", pkt->cmdString());
413 }
414
415 // Unless the requester explicitly said otherwise, generate an error if
416 // the functional request failed
417 if (!accessSucceeded && !pkt->suppressFuncError()) {
418 fatal("Ruby functional %s failed for address %#x\n",
419 pkt->isWrite() ? "write" : "read", pkt->getAddr());
420 }
421
422 // turn packet around to go back to requester if response expected
423 if (needsResponse) {
424 pkt->setFunctionalResponseStatus(accessSucceeded);
425 }
426
427 DPRINTF(RubyPort, "Functional access %s!\n",
428 accessSucceeded ? "successful":"failed");
429 }
430}
431
432void
433RubyPort::ruby_hit_callback(PacketPtr pkt)
434{
435 DPRINTF(RubyPort, "Hit callback for %s 0x%x\n", pkt->cmdString(),
436 pkt->getAddr());
437
438 // The packet was destined for memory and has not yet been turned
439 // into a response
440 assert(system->isMemAddr(pkt->getAddr()));
441 assert(pkt->isRequest());
442
443 // First we must retrieve the request port from the sender State
444 RubyPort::SenderState *senderState =
445 safe_cast<RubyPort::SenderState *>(pkt->popSenderState());
446 MemSlavePort *port = senderState->port;
447 assert(port != NULL);
448 delete senderState;
449
450 port->hitCallback(pkt);
451
452 trySendRetries();
453}
454
455void
456RubyPort::trySendRetries()
457{
458 //
459 // If we had to stall the MemSlavePorts, wake them up because the sequencer
460 // likely has free resources now.
461 //
462 if (!retryList.empty()) {
463 // Record the current list of ports to retry on a temporary list
464 // before calling sendRetryReq on those ports. sendRetryReq will cause
465 // an immediate retry, which may result in the ports being put back on
466 // the list. Therefore we want to clear the retryList before calling
467 // sendRetryReq.
468 std::vector<MemSlavePort *> curRetryList(retryList);
469
470 retryList.clear();
471
472 for (auto i = curRetryList.begin(); i != curRetryList.end(); ++i) {
473 DPRINTF(RubyPort,
474 "Sequencer may now be free. SendRetry to port %s\n",
475 (*i)->name());
476 (*i)->sendRetryReq();
477 }
478 }
479}
480
481void
482RubyPort::testDrainComplete()
483{
484 //If we weren't able to drain before, we might be able to now.
485 if (drainState() == DrainState::Draining) {
486 unsigned int drainCount = outstandingCount();
487 DPRINTF(Drain, "Drain count: %u\n", drainCount);
488 if (drainCount == 0) {
489 DPRINTF(Drain, "RubyPort done draining, signaling drain done\n");
490 signalDrainDone();
491 }
492 }
493}
494
495DrainState
496RubyPort::drain()
497{
498 if (isDeadlockEventScheduled()) {
499 descheduleDeadlockEvent();
500 }
501
502 //
503 // If the RubyPort is not empty, then it needs to clear all outstanding
504 // requests before it should call signalDrainDone()
505 //
506 DPRINTF(Config, "outstanding count %d\n", outstandingCount());
507 if (outstandingCount() > 0) {
508 DPRINTF(Drain, "RubyPort not drained\n");
509 return DrainState::Draining;
510 } else {
511 return DrainState::Drained;
512 }
513}
514
515void
516RubyPort::MemSlavePort::hitCallback(PacketPtr pkt)
517{
518 bool needsResponse = pkt->needsResponse();
519
520 // Unless specified at configuraiton, all responses except failed SC
521 // and Flush operations access M5 physical memory.
522 bool accessPhysMem = access_backing_store;
523
524 if (pkt->isLLSC()) {
525 if (pkt->isWrite()) {
526 if (pkt->req->getExtraData() != 0) {
527 //
528 // Successful SC packets convert to normal writes
529 //
530 pkt->convertScToWrite();
531 } else {
532 //
533 // Failed SC packets don't access physical memory and thus
534 // the RubyPort itself must convert it to a response.
535 //
536 accessPhysMem = false;
537 }
538 } else {
539 //
540 // All LL packets convert to normal loads so that M5 PhysMem does
541 // not lock the blocks.
542 //
543 pkt->convertLlToRead();
544 }
545 }
546
547 // Flush, acquire, release requests don't access physical memory
548 if (pkt->isFlush() || pkt->cmd == MemCmd::MemFenceReq) {
549 accessPhysMem = false;
550 }
551
552 if (pkt->req->isKernel()) {
553 accessPhysMem = false;
554 needsResponse = true;
555 }
556
557 DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse);
558
559 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
560 RubySystem *rs = ruby_port->m_ruby_system;
561 if (accessPhysMem) {
562 rs->getPhysMem()->access(pkt);
563 } else if (needsResponse) {
564 pkt->makeResponse();
565 }
566
567 // turn packet around to go back to requester if response expected
568 if (needsResponse) {
569 DPRINTF(RubyPort, "Sending packet back over port\n");
570 // Send a response in the same cycle. There is no need to delay the
571 // response because the response latency is already incurred in the
572 // Ruby protocol.
573 schedTimingResp(pkt, curTick());
574 } else {
575 delete pkt;
576 }
577
578 DPRINTF(RubyPort, "Hit callback done!\n");
579}
580
581AddrRangeList
582RubyPort::PioSlavePort::getAddrRanges() const
583{
584 // at the moment the assumption is that the master does not care
585 AddrRangeList ranges;
586 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
587
588 for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) {
589 ranges.splice(ranges.begin(),
590 ruby_port->master_ports[i]->getAddrRanges());
591 }
592 for (const auto M5_VAR_USED &r : ranges)
593 DPRINTF(RubyPort, "%s\n", r.to_string());
594 return ranges;
595}
596
597bool
598RubyPort::MemSlavePort::isPhysMemAddress(Addr addr) const
599{
600 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
601 return ruby_port->system->isMemAddr(addr);
602}
603
604void
605RubyPort::ruby_eviction_callback(Addr address)
606{
607 DPRINTF(RubyPort, "Sending invalidations.\n");
608 // Allocate the invalidate request and packet on the stack, as it is
609 // assumed they will not be modified or deleted by receivers.
610 // TODO: should this really be using funcMasterId?
| 1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009-2013 Advanced Micro Devices, Inc.
15 * Copyright (c) 2011 Mark D. Hill and David A. Wood
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
42#include "mem/ruby/system/RubyPort.hh"
43
44#include "cpu/testers/rubytest/RubyTester.hh"
45#include "debug/Config.hh"
46#include "debug/Drain.hh"
47#include "debug/Ruby.hh"
48#include "mem/protocol/AccessPermission.hh"
49#include "mem/ruby/slicc_interface/AbstractController.hh"
50#include "mem/simple_mem.hh"
51#include "sim/full_system.hh"
52#include "sim/system.hh"
53
54RubyPort::RubyPort(const Params *p)
55 : MemObject(p), m_ruby_system(p->ruby_system), m_version(p->version),
56 m_controller(NULL), m_mandatory_q_ptr(NULL),
57 m_usingRubyTester(p->using_ruby_tester), system(p->system),
58 pioMasterPort(csprintf("%s.pio-master-port", name()), this),
59 pioSlavePort(csprintf("%s.pio-slave-port", name()), this),
60 memMasterPort(csprintf("%s.mem-master-port", name()), this),
61 memSlavePort(csprintf("%s-mem-slave-port", name()), this,
62 p->ruby_system->getAccessBackingStore(), -1,
63 p->no_retry_on_stall),
64 gotAddrRanges(p->port_master_connection_count),
65 m_isCPUSequencer(p->is_cpu_sequencer)
66{
67 assert(m_version != -1);
68
69 // create the slave ports based on the number of connected ports
70 for (size_t i = 0; i < p->port_slave_connection_count; ++i) {
71 slave_ports.push_back(new MemSlavePort(csprintf("%s.slave%d", name(),
72 i), this, p->ruby_system->getAccessBackingStore(),
73 i, p->no_retry_on_stall));
74 }
75
76 // create the master ports based on the number of connected ports
77 for (size_t i = 0; i < p->port_master_connection_count; ++i) {
78 master_ports.push_back(new PioMasterPort(csprintf("%s.master%d",
79 name(), i), this));
80 }
81}
82
83void
84RubyPort::init()
85{
86 assert(m_controller != NULL);
87 m_mandatory_q_ptr = m_controller->getMandatoryQueue();
88}
89
90BaseMasterPort &
91RubyPort::getMasterPort(const std::string &if_name, PortID idx)
92{
93 if (if_name == "mem_master_port") {
94 return memMasterPort;
95 }
96
97 if (if_name == "pio_master_port") {
98 return pioMasterPort;
99 }
100
101 // used by the x86 CPUs to connect the interrupt PIO and interrupt slave
102 // port
103 if (if_name != "master") {
104 // pass it along to our super class
105 return MemObject::getMasterPort(if_name, idx);
106 } else {
107 if (idx >= static_cast<PortID>(master_ports.size())) {
108 panic("RubyPort::getMasterPort: unknown index %d\n", idx);
109 }
110
111 return *master_ports[idx];
112 }
113}
114
115BaseSlavePort &
116RubyPort::getSlavePort(const std::string &if_name, PortID idx)
117{
118 if (if_name == "mem_slave_port") {
119 return memSlavePort;
120 }
121
122 if (if_name == "pio_slave_port")
123 return pioSlavePort;
124
125 // used by the CPUs to connect the caches to the interconnect, and
126 // for the x86 case also the interrupt master
127 if (if_name != "slave") {
128 // pass it along to our super class
129 return MemObject::getSlavePort(if_name, idx);
130 } else {
131 if (idx >= static_cast<PortID>(slave_ports.size())) {
132 panic("RubyPort::getSlavePort: unknown index %d\n", idx);
133 }
134
135 return *slave_ports[idx];
136 }
137}
138
139RubyPort::PioMasterPort::PioMasterPort(const std::string &_name,
140 RubyPort *_port)
141 : QueuedMasterPort(_name, _port, reqQueue, snoopRespQueue),
142 reqQueue(*_port, *this), snoopRespQueue(*_port, *this)
143{
144 DPRINTF(RubyPort, "Created master pioport on sequencer %s\n", _name);
145}
146
147RubyPort::PioSlavePort::PioSlavePort(const std::string &_name,
148 RubyPort *_port)
149 : QueuedSlavePort(_name, _port, queue), queue(*_port, *this)
150{
151 DPRINTF(RubyPort, "Created slave pioport on sequencer %s\n", _name);
152}
153
154RubyPort::MemMasterPort::MemMasterPort(const std::string &_name,
155 RubyPort *_port)
156 : QueuedMasterPort(_name, _port, reqQueue, snoopRespQueue),
157 reqQueue(*_port, *this), snoopRespQueue(*_port, *this)
158{
159 DPRINTF(RubyPort, "Created master memport on ruby sequencer %s\n", _name);
160}
161
162RubyPort::MemSlavePort::MemSlavePort(const std::string &_name, RubyPort *_port,
163 bool _access_backing_store, PortID id,
164 bool _no_retry_on_stall)
165 : QueuedSlavePort(_name, _port, queue, id), queue(*_port, *this),
166 access_backing_store(_access_backing_store),
167 no_retry_on_stall(_no_retry_on_stall)
168{
169 DPRINTF(RubyPort, "Created slave memport on ruby sequencer %s\n", _name);
170}
171
172bool
173RubyPort::PioMasterPort::recvTimingResp(PacketPtr pkt)
174{
175 RubyPort *rp = static_cast<RubyPort *>(&owner);
176 DPRINTF(RubyPort, "Response for address: 0x%#x\n", pkt->getAddr());
177
178 // send next cycle
179 rp->pioSlavePort.schedTimingResp(
180 pkt, curTick() + rp->m_ruby_system->clockPeriod());
181 return true;
182}
183
184bool RubyPort::MemMasterPort::recvTimingResp(PacketPtr pkt)
185{
186 // got a response from a device
187 assert(pkt->isResponse());
188
189 // First we must retrieve the request port from the sender State
190 RubyPort::SenderState *senderState =
191 safe_cast<RubyPort::SenderState *>(pkt->popSenderState());
192 MemSlavePort *port = senderState->port;
193 assert(port != NULL);
194 delete senderState;
195
196 // In FS mode, ruby memory will receive pio responses from devices
197 // and it must forward these responses back to the particular CPU.
198 DPRINTF(RubyPort, "Pio response for address %#x, going to %s\n",
199 pkt->getAddr(), port->name());
200
201 // attempt to send the response in the next cycle
202 RubyPort *rp = static_cast<RubyPort *>(&owner);
203 port->schedTimingResp(pkt, curTick() + rp->m_ruby_system->clockPeriod());
204
205 return true;
206}
207
208bool
209RubyPort::PioSlavePort::recvTimingReq(PacketPtr pkt)
210{
211 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
212
213 for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) {
214 AddrRangeList l = ruby_port->master_ports[i]->getAddrRanges();
215 for (auto it = l.begin(); it != l.end(); ++it) {
216 if (it->contains(pkt->getAddr())) {
217 // generally it is not safe to assume success here as
218 // the port could be blocked
219 bool M5_VAR_USED success =
220 ruby_port->master_ports[i]->sendTimingReq(pkt);
221 assert(success);
222 return true;
223 }
224 }
225 }
226 panic("Should never reach here!\n");
227}
228
229Tick
230RubyPort::PioSlavePort::recvAtomic(PacketPtr pkt)
231{
232 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
233 // Only atomic_noncaching mode supported!
234 if (!ruby_port->system->bypassCaches()) {
235 panic("Ruby supports atomic accesses only in noncaching mode\n");
236 }
237
238 for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) {
239 AddrRangeList l = ruby_port->master_ports[i]->getAddrRanges();
240 for (auto it = l.begin(); it != l.end(); ++it) {
241 if (it->contains(pkt->getAddr())) {
242 return ruby_port->master_ports[i]->sendAtomic(pkt);
243 }
244 }
245 }
246 panic("Could not find address in Ruby PIO address ranges!\n");
247}
248
249bool
250RubyPort::MemSlavePort::recvTimingReq(PacketPtr pkt)
251{
252 DPRINTF(RubyPort, "Timing request for address %#x on port %d\n",
253 pkt->getAddr(), id);
254 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
255
256 if (pkt->cacheResponding())
257 panic("RubyPort should never see request with the "
258 "cacheResponding flag set\n");
259
260 // ruby doesn't support cache maintenance operations at the
261 // moment, as a workaround, we respond right away
262 if (pkt->req->isCacheMaintenance()) {
263 warn_once("Cache maintenance operations are not supported in Ruby.\n");
264 pkt->makeResponse();
265 schedTimingResp(pkt, curTick());
266 return true;
267 }
268 // Check for pio requests and directly send them to the dedicated
269 // pio port.
270 if (pkt->cmd != MemCmd::MemFenceReq) {
271 if (!isPhysMemAddress(pkt->getAddr())) {
272 assert(ruby_port->memMasterPort.isConnected());
273 DPRINTF(RubyPort, "Request address %#x assumed to be a "
274 "pio address\n", pkt->getAddr());
275
276 // Save the port in the sender state object to be used later to
277 // route the response
278 pkt->pushSenderState(new SenderState(this));
279
280 // send next cycle
281 RubySystem *rs = ruby_port->m_ruby_system;
282 ruby_port->memMasterPort.schedTimingReq(pkt,
283 curTick() + rs->clockPeriod());
284 return true;
285 }
286
287 assert(getOffset(pkt->getAddr()) + pkt->getSize() <=
288 RubySystem::getBlockSizeBytes());
289 }
290
291 // Submit the ruby request
292 RequestStatus requestStatus = ruby_port->makeRequest(pkt);
293
294 // If the request successfully issued then we should return true.
295 // Otherwise, we need to tell the port to retry at a later point
296 // and return false.
297 if (requestStatus == RequestStatus_Issued) {
298 // Save the port in the sender state object to be used later to
299 // route the response
300 pkt->pushSenderState(new SenderState(this));
301
302 DPRINTF(RubyPort, "Request %s address %#x issued\n", pkt->cmdString(),
303 pkt->getAddr());
304 return true;
305 }
306
307 if (pkt->cmd != MemCmd::MemFenceReq) {
308 DPRINTF(RubyPort,
309 "Request %s for address %#x did not issue because %s\n",
310 pkt->cmdString(), pkt->getAddr(),
311 RequestStatus_to_string(requestStatus));
312 }
313
314 addToRetryList();
315
316 return false;
317}
318
319Tick
320RubyPort::MemSlavePort::recvAtomic(PacketPtr pkt)
321{
322 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
323 // Only atomic_noncaching mode supported!
324 if (!ruby_port->system->bypassCaches()) {
325 panic("Ruby supports atomic accesses only in noncaching mode\n");
326 }
327
328 // Check for pio requests and directly send them to the dedicated
329 // pio port.
330 if (pkt->cmd != MemCmd::MemFenceReq) {
331 if (!isPhysMemAddress(pkt->getAddr())) {
332 assert(ruby_port->memMasterPort.isConnected());
333 DPRINTF(RubyPort, "Request address %#x assumed to be a "
334 "pio address\n", pkt->getAddr());
335
336 // Save the port in the sender state object to be used later to
337 // route the response
338 pkt->pushSenderState(new SenderState(this));
339
340 // send next cycle
341 Tick req_ticks = ruby_port->memMasterPort.sendAtomic(pkt);
342 return ruby_port->ticksToCycles(req_ticks);
343 }
344
345 assert(getOffset(pkt->getAddr()) + pkt->getSize() <=
346 RubySystem::getBlockSizeBytes());
347 }
348
349 // Find appropriate directory for address
350 // This assumes that protocols have a Directory machine,
351 // which has its memPort hooked up to memory. This can
352 // fail for some custom protocols.
353 MachineID id = ruby_port->m_controller->mapAddressToMachine(
354 pkt->getAddr(), MachineType_Directory);
355 RubySystem *rs = ruby_port->m_ruby_system;
356 AbstractController *directory =
357 rs->m_abstract_controls[id.getType()][id.getNum()];
358 return directory->recvAtomic(pkt);
359}
360
361void
362RubyPort::MemSlavePort::addToRetryList()
363{
364 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
365
366 //
367 // Unless the requestor do not want retries (e.g., the Ruby tester),
368 // record the stalled M5 port for later retry when the sequencer
369 // becomes free.
370 //
371 if (!no_retry_on_stall && !ruby_port->onRetryList(this)) {
372 ruby_port->addToRetryList(this);
373 }
374}
375
376void
377RubyPort::MemSlavePort::recvFunctional(PacketPtr pkt)
378{
379 DPRINTF(RubyPort, "Functional access for address: %#x\n", pkt->getAddr());
380
381 RubyPort *rp M5_VAR_USED = static_cast<RubyPort *>(&owner);
382 RubySystem *rs = rp->m_ruby_system;
383
384 // Check for pio requests and directly send them to the dedicated
385 // pio port.
386 if (!isPhysMemAddress(pkt->getAddr())) {
387 DPRINTF(RubyPort, "Pio Request for address: 0x%#x\n", pkt->getAddr());
388 assert(rp->pioMasterPort.isConnected());
389 rp->pioMasterPort.sendFunctional(pkt);
390 return;
391 }
392
393 assert(pkt->getAddr() + pkt->getSize() <=
394 makeLineAddress(pkt->getAddr()) + RubySystem::getBlockSizeBytes());
395
396 if (access_backing_store) {
397 // The attached physmem contains the official version of data.
398 // The following command performs the real functional access.
399 // This line should be removed once Ruby supplies the official version
400 // of data.
401 rs->getPhysMem()->functionalAccess(pkt);
402 } else {
403 bool accessSucceeded = false;
404 bool needsResponse = pkt->needsResponse();
405
406 // Do the functional access on ruby memory
407 if (pkt->isRead()) {
408 accessSucceeded = rs->functionalRead(pkt);
409 } else if (pkt->isWrite()) {
410 accessSucceeded = rs->functionalWrite(pkt);
411 } else {
412 panic("Unsupported functional command %s\n", pkt->cmdString());
413 }
414
415 // Unless the requester explicitly said otherwise, generate an error if
416 // the functional request failed
417 if (!accessSucceeded && !pkt->suppressFuncError()) {
418 fatal("Ruby functional %s failed for address %#x\n",
419 pkt->isWrite() ? "write" : "read", pkt->getAddr());
420 }
421
422 // turn packet around to go back to requester if response expected
423 if (needsResponse) {
424 pkt->setFunctionalResponseStatus(accessSucceeded);
425 }
426
427 DPRINTF(RubyPort, "Functional access %s!\n",
428 accessSucceeded ? "successful":"failed");
429 }
430}
431
432void
433RubyPort::ruby_hit_callback(PacketPtr pkt)
434{
435 DPRINTF(RubyPort, "Hit callback for %s 0x%x\n", pkt->cmdString(),
436 pkt->getAddr());
437
438 // The packet was destined for memory and has not yet been turned
439 // into a response
440 assert(system->isMemAddr(pkt->getAddr()));
441 assert(pkt->isRequest());
442
443 // First we must retrieve the request port from the sender State
444 RubyPort::SenderState *senderState =
445 safe_cast<RubyPort::SenderState *>(pkt->popSenderState());
446 MemSlavePort *port = senderState->port;
447 assert(port != NULL);
448 delete senderState;
449
450 port->hitCallback(pkt);
451
452 trySendRetries();
453}
454
455void
456RubyPort::trySendRetries()
457{
458 //
459 // If we had to stall the MemSlavePorts, wake them up because the sequencer
460 // likely has free resources now.
461 //
462 if (!retryList.empty()) {
463 // Record the current list of ports to retry on a temporary list
464 // before calling sendRetryReq on those ports. sendRetryReq will cause
465 // an immediate retry, which may result in the ports being put back on
466 // the list. Therefore we want to clear the retryList before calling
467 // sendRetryReq.
468 std::vector<MemSlavePort *> curRetryList(retryList);
469
470 retryList.clear();
471
472 for (auto i = curRetryList.begin(); i != curRetryList.end(); ++i) {
473 DPRINTF(RubyPort,
474 "Sequencer may now be free. SendRetry to port %s\n",
475 (*i)->name());
476 (*i)->sendRetryReq();
477 }
478 }
479}
480
481void
482RubyPort::testDrainComplete()
483{
484 //If we weren't able to drain before, we might be able to now.
485 if (drainState() == DrainState::Draining) {
486 unsigned int drainCount = outstandingCount();
487 DPRINTF(Drain, "Drain count: %u\n", drainCount);
488 if (drainCount == 0) {
489 DPRINTF(Drain, "RubyPort done draining, signaling drain done\n");
490 signalDrainDone();
491 }
492 }
493}
494
495DrainState
496RubyPort::drain()
497{
498 if (isDeadlockEventScheduled()) {
499 descheduleDeadlockEvent();
500 }
501
502 //
503 // If the RubyPort is not empty, then it needs to clear all outstanding
504 // requests before it should call signalDrainDone()
505 //
506 DPRINTF(Config, "outstanding count %d\n", outstandingCount());
507 if (outstandingCount() > 0) {
508 DPRINTF(Drain, "RubyPort not drained\n");
509 return DrainState::Draining;
510 } else {
511 return DrainState::Drained;
512 }
513}
514
515void
516RubyPort::MemSlavePort::hitCallback(PacketPtr pkt)
517{
518 bool needsResponse = pkt->needsResponse();
519
520 // Unless specified at configuraiton, all responses except failed SC
521 // and Flush operations access M5 physical memory.
522 bool accessPhysMem = access_backing_store;
523
524 if (pkt->isLLSC()) {
525 if (pkt->isWrite()) {
526 if (pkt->req->getExtraData() != 0) {
527 //
528 // Successful SC packets convert to normal writes
529 //
530 pkt->convertScToWrite();
531 } else {
532 //
533 // Failed SC packets don't access physical memory and thus
534 // the RubyPort itself must convert it to a response.
535 //
536 accessPhysMem = false;
537 }
538 } else {
539 //
540 // All LL packets convert to normal loads so that M5 PhysMem does
541 // not lock the blocks.
542 //
543 pkt->convertLlToRead();
544 }
545 }
546
547 // Flush, acquire, release requests don't access physical memory
548 if (pkt->isFlush() || pkt->cmd == MemCmd::MemFenceReq) {
549 accessPhysMem = false;
550 }
551
552 if (pkt->req->isKernel()) {
553 accessPhysMem = false;
554 needsResponse = true;
555 }
556
557 DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse);
558
559 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
560 RubySystem *rs = ruby_port->m_ruby_system;
561 if (accessPhysMem) {
562 rs->getPhysMem()->access(pkt);
563 } else if (needsResponse) {
564 pkt->makeResponse();
565 }
566
567 // turn packet around to go back to requester if response expected
568 if (needsResponse) {
569 DPRINTF(RubyPort, "Sending packet back over port\n");
570 // Send a response in the same cycle. There is no need to delay the
571 // response because the response latency is already incurred in the
572 // Ruby protocol.
573 schedTimingResp(pkt, curTick());
574 } else {
575 delete pkt;
576 }
577
578 DPRINTF(RubyPort, "Hit callback done!\n");
579}
580
581AddrRangeList
582RubyPort::PioSlavePort::getAddrRanges() const
583{
584 // at the moment the assumption is that the master does not care
585 AddrRangeList ranges;
586 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
587
588 for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) {
589 ranges.splice(ranges.begin(),
590 ruby_port->master_ports[i]->getAddrRanges());
591 }
592 for (const auto M5_VAR_USED &r : ranges)
593 DPRINTF(RubyPort, "%s\n", r.to_string());
594 return ranges;
595}
596
597bool
598RubyPort::MemSlavePort::isPhysMemAddress(Addr addr) const
599{
600 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
601 return ruby_port->system->isMemAddr(addr);
602}
603
604void
605RubyPort::ruby_eviction_callback(Addr address)
606{
607 DPRINTF(RubyPort, "Sending invalidations.\n");
608 // Allocate the invalidate request and packet on the stack, as it is
609 // assumed they will not be modified or deleted by receivers.
610 // TODO: should this really be using funcMasterId?
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