RubyPort.cc (8922:17f037ad8918) | RubyPort.cc (8923:820111f58fbb) |
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1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 31 unchanged lines hidden (view full) --- 40 */ 41 42#include "cpu/testers/rubytest/RubyTester.hh" 43#include "debug/Config.hh" 44#include "debug/Ruby.hh" 45#include "mem/protocol/AccessPermission.hh" 46#include "mem/ruby/slicc_interface/AbstractController.hh" 47#include "mem/ruby/system/RubyPort.hh" | 1/* 2 * Copyright (c) 2012 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 31 unchanged lines hidden (view full) --- 40 */ 41 42#include "cpu/testers/rubytest/RubyTester.hh" 43#include "debug/Config.hh" 44#include "debug/Ruby.hh" 45#include "mem/protocol/AccessPermission.hh" 46#include "mem/ruby/slicc_interface/AbstractController.hh" 47#include "mem/ruby/system/RubyPort.hh" |
48#include "sim/system.hh" |
|
48 49RubyPort::RubyPort(const Params *p) 50 : MemObject(p), m_version(p->version), m_controller(NULL), 51 m_mandatory_q_ptr(NULL), 52 pio_port(csprintf("%s-pio-port", name()), this), 53 m_usingRubyTester(p->using_ruby_tester), m_request_cnt(0), | 49 50RubyPort::RubyPort(const Params *p) 51 : MemObject(p), m_version(p->version), m_controller(NULL), 52 m_mandatory_q_ptr(NULL), 53 pio_port(csprintf("%s-pio-port", name()), this), 54 m_usingRubyTester(p->using_ruby_tester), m_request_cnt(0), |
54 physMemPort(csprintf("%s-physMemPort", name()), this), 55 drainEvent(NULL), physmem(p->physmem), ruby_system(p->ruby_system), | 55 drainEvent(NULL), ruby_system(p->ruby_system), system(p->system), |
56 waitingOnSequencer(false), access_phys_mem(p->access_phys_mem) 57{ 58 assert(m_version != -1); 59 60 // create the slave ports based on the number of connected ports 61 for (size_t i = 0; i < p->port_slave_connection_count; ++i) { 62 slave_ports.push_back(new M5Port(csprintf("%s-slave%d", name(), i), 63 this, ruby_system, access_phys_mem)); --- 15 unchanged lines hidden (view full) --- 79 80MasterPort & 81RubyPort::getMasterPort(const std::string &if_name, int idx) 82{ 83 if (if_name == "pio_port") { 84 return pio_port; 85 } 86 | 56 waitingOnSequencer(false), access_phys_mem(p->access_phys_mem) 57{ 58 assert(m_version != -1); 59 60 // create the slave ports based on the number of connected ports 61 for (size_t i = 0; i < p->port_slave_connection_count; ++i) { 62 slave_ports.push_back(new M5Port(csprintf("%s-slave%d", name(), i), 63 this, ruby_system, access_phys_mem)); --- 15 unchanged lines hidden (view full) --- 79 80MasterPort & 81RubyPort::getMasterPort(const std::string &if_name, int idx) 82{ 83 if (if_name == "pio_port") { 84 return pio_port; 85 } 86 |
87 if (if_name == "physMemPort") { 88 return physMemPort; 89 } 90 | |
91 // used by the x86 CPUs to connect the interrupt PIO and interrupt slave 92 // port 93 if (if_name != "master") { 94 // pass it along to our super class 95 return MemObject::getMasterPort(if_name, idx); 96 } else { 97 if (idx >= static_cast<int>(master_ports.size())) { 98 panic("RubyPort::getMasterPort: unknown index %d\n", idx); --- 367 unchanged lines hidden (view full) --- 466 pkt->isWrite() ? "write" : "read", pkt->getAddr()); 467 } 468 469 if (access_phys_mem) { 470 // The attached physmem contains the official version of data. 471 // The following command performs the real functional access. 472 // This line should be removed once Ruby supplies the official version 473 // of data. | 87 // used by the x86 CPUs to connect the interrupt PIO and interrupt slave 88 // port 89 if (if_name != "master") { 90 // pass it along to our super class 91 return MemObject::getMasterPort(if_name, idx); 92 } else { 93 if (idx >= static_cast<int>(master_ports.size())) { 94 panic("RubyPort::getMasterPort: unknown index %d\n", idx); --- 367 unchanged lines hidden (view full) --- 462 pkt->isWrite() ? "write" : "read", pkt->getAddr()); 463 } 464 465 if (access_phys_mem) { 466 // The attached physmem contains the official version of data. 467 // The following command performs the real functional access. 468 // This line should be removed once Ruby supplies the official version 469 // of data. |
474 ruby_port->physMemPort.sendFunctional(pkt); | 470 ruby_port->system->physmem->doFunctionalAccess(pkt); |
475 } 476 477 // turn packet around to go back to requester if response expected 478 if (needsResponse) { 479 pkt->setFunctionalResponseStatus(accessSucceeded); 480 481 // @todo There should not be a reverse call since the response is 482 // communicated through the packet pointer --- 80 unchanged lines hidden (view full) --- 563 // To simplify the draining process, the sequencer's deadlock detection 564 // event should have been descheduled. 565 assert(isDeadlockEventScheduled() == false); 566 567 if (pio_port.isConnected()) { 568 count += pio_port.drain(de); 569 DPRINTF(Config, "count after pio check %d\n", count); 570 } | 471 } 472 473 // turn packet around to go back to requester if response expected 474 if (needsResponse) { 475 pkt->setFunctionalResponseStatus(accessSucceeded); 476 477 // @todo There should not be a reverse call since the response is 478 // communicated through the packet pointer --- 80 unchanged lines hidden (view full) --- 559 // To simplify the draining process, the sequencer's deadlock detection 560 // event should have been descheduled. 561 assert(isDeadlockEventScheduled() == false); 562 563 if (pio_port.isConnected()) { 564 count += pio_port.drain(de); 565 DPRINTF(Config, "count after pio check %d\n", count); 566 } |
571 if (physMemPort.isConnected()) { 572 count += physMemPort.drain(de); 573 DPRINTF(Config, "count after physmem check %d\n", count); 574 } | |
575 576 for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) { 577 count += (*p)->drain(de); 578 DPRINTF(Config, "count after slave port check %d\n", count); 579 } 580 581 for (std::vector<PioPort*>::iterator p = master_ports.begin(); 582 p != master_ports.end(); ++p) { --- 66 unchanged lines hidden (view full) --- 649 // 650 if (pkt->isFlush()) { 651 accessPhysMem = false; 652 } 653 654 DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse); 655 656 if (accessPhysMem) { | 567 568 for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) { 569 count += (*p)->drain(de); 570 DPRINTF(Config, "count after slave port check %d\n", count); 571 } 572 573 for (std::vector<PioPort*>::iterator p = master_ports.begin(); 574 p != master_ports.end(); ++p) { --- 66 unchanged lines hidden (view full) --- 641 // 642 if (pkt->isFlush()) { 643 accessPhysMem = false; 644 } 645 646 DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse); 647 648 if (accessPhysMem) { |
657 ruby_port->physMemPort.sendAtomic(pkt); | 649 ruby_port->system->physmem->doAtomicAccess(pkt); |
658 } else if (needsResponse) { 659 pkt->makeResponse(); 660 } 661 662 // turn packet around to go back to requester if response expected 663 if (needsResponse) { 664 DPRINTF(RubyPort, "Sending packet back over port\n"); 665 sendNextCycle(pkt); --- 25 unchanged lines hidden (view full) --- 691 // at the moment the assumption is that the master does not care 692 AddrRangeList ranges; 693 return ranges; 694} 695 696bool 697RubyPort::M5Port::isPhysMemAddress(Addr addr) 698{ | 650 } else if (needsResponse) { 651 pkt->makeResponse(); 652 } 653 654 // turn packet around to go back to requester if response expected 655 if (needsResponse) { 656 DPRINTF(RubyPort, "Sending packet back over port\n"); 657 sendNextCycle(pkt); --- 25 unchanged lines hidden (view full) --- 683 // at the moment the assumption is that the master does not care 684 AddrRangeList ranges; 685 return ranges; 686} 687 688bool 689RubyPort::M5Port::isPhysMemAddress(Addr addr) 690{ |
699 AddrRangeList physMemAddrList = 700 ruby_port->physMemPort.getSlavePort().getAddrRanges(); 701 for (AddrRangeIter iter = physMemAddrList.begin(); 702 iter != physMemAddrList.end(); 703 iter++) { 704 if (addr >= iter->start && addr <= iter->end) { 705 DPRINTF(RubyPort, "Request found in %#llx - %#llx range\n", 706 iter->start, iter->end); 707 return true; 708 } 709 } 710 return false; | 691 return ruby_port->system->isMemory(addr); |
711} 712 713unsigned 714RubyPort::M5Port::deviceBlockSize() const 715{ 716 return (unsigned) RubySystem::getBlockSizeBytes(); 717} 718 --- 13 unchanged lines hidden --- | 692} 693 694unsigned 695RubyPort::M5Port::deviceBlockSize() const 696{ 697 return (unsigned) RubySystem::getBlockSizeBytes(); 698} 699 --- 13 unchanged lines hidden --- |