1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009-2013 Advanced Micro Devices, Inc.
15 * Copyright (c) 2011 Mark D. Hill and David A. Wood
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
42#include "mem/ruby/system/RubyPort.hh"
43
44#include "cpu/testers/rubytest/RubyTester.hh"
45#include "debug/Config.hh"
46#include "debug/Drain.hh"
47#include "debug/Ruby.hh"
48#include "mem/protocol/AccessPermission.hh"
49#include "mem/ruby/slicc_interface/AbstractController.hh"
50#include "mem/simple_mem.hh"
51#include "sim/full_system.hh"
52#include "sim/system.hh"
53
54RubyPort::RubyPort(const Params *p)
55 : MemObject(p), m_ruby_system(p->ruby_system), m_version(p->version),
56 m_controller(NULL), m_mandatory_q_ptr(NULL),
57 m_usingRubyTester(p->using_ruby_tester), system(p->system),
58 pioMasterPort(csprintf("%s.pio-master-port", name()), this),
59 pioSlavePort(csprintf("%s.pio-slave-port", name()), this),
60 memMasterPort(csprintf("%s.mem-master-port", name()), this),
61 memSlavePort(csprintf("%s-mem-slave-port", name()), this,
62 p->ruby_system->getAccessBackingStore(), -1,
63 p->no_retry_on_stall),
64 gotAddrRanges(p->port_master_connection_count),
65 m_isCPUSequencer(p->is_cpu_sequencer)
66{
67 assert(m_version != -1);
68
69 // create the slave ports based on the number of connected ports
70 for (size_t i = 0; i < p->port_slave_connection_count; ++i) {
71 slave_ports.push_back(new MemSlavePort(csprintf("%s.slave%d", name(),
72 i), this, p->ruby_system->getAccessBackingStore(),
73 i, p->no_retry_on_stall));
74 }
75
76 // create the master ports based on the number of connected ports
77 for (size_t i = 0; i < p->port_master_connection_count; ++i) {
78 master_ports.push_back(new PioMasterPort(csprintf("%s.master%d",
79 name(), i), this));
80 }
81}
82
83void
84RubyPort::init()
85{
86 assert(m_controller != NULL);
87 m_mandatory_q_ptr = m_controller->getMandatoryQueue();
88}
89
90BaseMasterPort &
91RubyPort::getMasterPort(const std::string &if_name, PortID idx)
92{
93 if (if_name == "mem_master_port") {
94 return memMasterPort;
95 }
96
97 if (if_name == "pio_master_port") {
98 return pioMasterPort;
99 }
100
101 // used by the x86 CPUs to connect the interrupt PIO and interrupt slave
102 // port
103 if (if_name != "master") {
104 // pass it along to our super class
105 return MemObject::getMasterPort(if_name, idx);
106 } else {
107 if (idx >= static_cast<PortID>(master_ports.size())) {
108 panic("RubyPort::getMasterPort: unknown index %d\n", idx);
109 }
110
111 return *master_ports[idx];
112 }
113}
114
115BaseSlavePort &
116RubyPort::getSlavePort(const std::string &if_name, PortID idx)
117{
118 if (if_name == "mem_slave_port") {
119 return memSlavePort;
120 }
121
122 if (if_name == "pio_slave_port")
123 return pioSlavePort;
124
125 // used by the CPUs to connect the caches to the interconnect, and
126 // for the x86 case also the interrupt master
127 if (if_name != "slave") {
128 // pass it along to our super class
129 return MemObject::getSlavePort(if_name, idx);
130 } else {
131 if (idx >= static_cast<PortID>(slave_ports.size())) {
132 panic("RubyPort::getSlavePort: unknown index %d\n", idx);
133 }
134
135 return *slave_ports[idx];
136 }
137}
138
139RubyPort::PioMasterPort::PioMasterPort(const std::string &_name,
140 RubyPort *_port)
141 : QueuedMasterPort(_name, _port, reqQueue, snoopRespQueue),
142 reqQueue(*_port, *this), snoopRespQueue(*_port, *this)
143{
144 DPRINTF(RubyPort, "Created master pioport on sequencer %s\n", _name);
145}
146
147RubyPort::PioSlavePort::PioSlavePort(const std::string &_name,
148 RubyPort *_port)
149 : QueuedSlavePort(_name, _port, queue), queue(*_port, *this)
150{
151 DPRINTF(RubyPort, "Created slave pioport on sequencer %s\n", _name);
152}
153
154RubyPort::MemMasterPort::MemMasterPort(const std::string &_name,
155 RubyPort *_port)
156 : QueuedMasterPort(_name, _port, reqQueue, snoopRespQueue),
157 reqQueue(*_port, *this), snoopRespQueue(*_port, *this)
158{
159 DPRINTF(RubyPort, "Created master memport on ruby sequencer %s\n", _name);
160}
161
162RubyPort::MemSlavePort::MemSlavePort(const std::string &_name, RubyPort *_port,
163 bool _access_backing_store, PortID id,
164 bool _no_retry_on_stall)
165 : QueuedSlavePort(_name, _port, queue, id), queue(*_port, *this),
166 access_backing_store(_access_backing_store),
167 no_retry_on_stall(_no_retry_on_stall)
168{
169 DPRINTF(RubyPort, "Created slave memport on ruby sequencer %s\n", _name);
170}
171
172bool
173RubyPort::PioMasterPort::recvTimingResp(PacketPtr pkt)
174{
175 RubyPort *rp = static_cast<RubyPort *>(&owner);
176 DPRINTF(RubyPort, "Response for address: 0x%#x\n", pkt->getAddr());
177
178 // send next cycle
179 rp->pioSlavePort.schedTimingResp(
180 pkt, curTick() + rp->m_ruby_system->clockPeriod());
181 return true;
182}
183
184bool RubyPort::MemMasterPort::recvTimingResp(PacketPtr pkt)
185{
186 // got a response from a device
187 assert(pkt->isResponse());
188
189 // First we must retrieve the request port from the sender State
190 RubyPort::SenderState *senderState =
191 safe_cast<RubyPort::SenderState *>(pkt->popSenderState());
192 MemSlavePort *port = senderState->port;
193 assert(port != NULL);
194 delete senderState;
195
196 // In FS mode, ruby memory will receive pio responses from devices
197 // and it must forward these responses back to the particular CPU.
198 DPRINTF(RubyPort, "Pio response for address %#x, going to %s\n",
199 pkt->getAddr(), port->name());
200
201 // attempt to send the response in the next cycle
202 RubyPort *rp = static_cast<RubyPort *>(&owner);
203 port->schedTimingResp(pkt, curTick() + rp->m_ruby_system->clockPeriod());
204
205 return true;
206}
207
208bool
209RubyPort::PioSlavePort::recvTimingReq(PacketPtr pkt)
210{
211 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
212
213 for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) {
214 AddrRangeList l = ruby_port->master_ports[i]->getAddrRanges();
215 for (auto it = l.begin(); it != l.end(); ++it) {
216 if (it->contains(pkt->getAddr())) {
217 // generally it is not safe to assume success here as
218 // the port could be blocked
219 bool M5_VAR_USED success =
220 ruby_port->master_ports[i]->sendTimingReq(pkt);
221 assert(success);
222 return true;
223 }
224 }
225 }
226 panic("Should never reach here!\n");
227}
228
229bool
230RubyPort::MemSlavePort::recvTimingReq(PacketPtr pkt)
231{
232 DPRINTF(RubyPort, "Timing request for address %#x on port %d\n",
233 pkt->getAddr(), id);
234 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
235
236 if (pkt->cacheResponding())
237 panic("RubyPort should never see request with the "
238 "cacheResponding flag set\n");
239
240 // ruby doesn't support cache maintenance operations at the
241 // moment, as a workaround, we respond right away
242 if (pkt->req->isCacheMaintenance()) {
243 warn_once("Cache maintenance operations are not supported in Ruby.\n");
244 pkt->makeResponse();
245 schedTimingResp(pkt, curTick());
246 return true;
247 }
248 // Check for pio requests and directly send them to the dedicated
249 // pio port.
250 if (pkt->cmd != MemCmd::MemFenceReq) {
251 if (!isPhysMemAddress(pkt->getAddr())) {
252 assert(ruby_port->memMasterPort.isConnected());
253 DPRINTF(RubyPort, "Request address %#x assumed to be a "
254 "pio address\n", pkt->getAddr());
255
256 // Save the port in the sender state object to be used later to
257 // route the response
258 pkt->pushSenderState(new SenderState(this));
259
260 // send next cycle
261 RubySystem *rs = ruby_port->m_ruby_system;
262 ruby_port->memMasterPort.schedTimingReq(pkt,
263 curTick() + rs->clockPeriod());
264 return true;
265 }
266
267 assert(getOffset(pkt->getAddr()) + pkt->getSize() <=
268 RubySystem::getBlockSizeBytes());
269 }
270
271 // Submit the ruby request
272 RequestStatus requestStatus = ruby_port->makeRequest(pkt);
273
274 // If the request successfully issued then we should return true.
275 // Otherwise, we need to tell the port to retry at a later point
276 // and return false.
277 if (requestStatus == RequestStatus_Issued) {
278 // Save the port in the sender state object to be used later to
279 // route the response
280 pkt->pushSenderState(new SenderState(this));
281
282 DPRINTF(RubyPort, "Request %s 0x%x issued\n", pkt->cmdString(),
283 pkt->getAddr());
284 return true;
285 }
286
287 if (pkt->cmd != MemCmd::MemFenceReq) {
288 DPRINTF(RubyPort,
289 "Request for address %#x did not issued because %s\n",
290 pkt->getAddr(), RequestStatus_to_string(requestStatus));
291 }
292
293 addToRetryList();
294
295 return false;
296}
297
298void
299RubyPort::MemSlavePort::addToRetryList()
300{
301 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
302
303 //
304 // Unless the requestor do not want retries (e.g., the Ruby tester),
305 // record the stalled M5 port for later retry when the sequencer
306 // becomes free.
307 //
308 if (!no_retry_on_stall && !ruby_port->onRetryList(this)) {
309 ruby_port->addToRetryList(this);
310 }
311}
312
313void
314RubyPort::MemSlavePort::recvFunctional(PacketPtr pkt)
315{
316 DPRINTF(RubyPort, "Functional access for address: %#x\n", pkt->getAddr());
317
318 RubyPort *rp M5_VAR_USED = static_cast<RubyPort *>(&owner);
319 RubySystem *rs = rp->m_ruby_system;
320
321 // Check for pio requests and directly send them to the dedicated
322 // pio port.
323 if (!isPhysMemAddress(pkt->getAddr())) {
324 DPRINTF(RubyPort, "Pio Request for address: 0x%#x\n", pkt->getAddr());
325 assert(rp->pioMasterPort.isConnected());
326 rp->pioMasterPort.sendFunctional(pkt);
327 return;
328 }
329
330 assert(pkt->getAddr() + pkt->getSize() <=
331 makeLineAddress(pkt->getAddr()) + RubySystem::getBlockSizeBytes());
332
333 if (access_backing_store) {
334 // The attached physmem contains the official version of data.
335 // The following command performs the real functional access.
336 // This line should be removed once Ruby supplies the official version
337 // of data.
338 rs->getPhysMem()->functionalAccess(pkt);
339 } else {
340 bool accessSucceeded = false;
341 bool needsResponse = pkt->needsResponse();
342
343 // Do the functional access on ruby memory
344 if (pkt->isRead()) {
345 accessSucceeded = rs->functionalRead(pkt);
346 } else if (pkt->isWrite()) {
347 accessSucceeded = rs->functionalWrite(pkt);
348 } else {
349 panic("Unsupported functional command %s\n", pkt->cmdString());
350 }
351
352 // Unless the requester explicitly said otherwise, generate an error if
353 // the functional request failed
354 if (!accessSucceeded && !pkt->suppressFuncError()) {
355 fatal("Ruby functional %s failed for address %#x\n",
356 pkt->isWrite() ? "write" : "read", pkt->getAddr());
357 }
358
359 // turn packet around to go back to requester if response expected
360 if (needsResponse) {
361 pkt->setFunctionalResponseStatus(accessSucceeded);
362 }
363
364 DPRINTF(RubyPort, "Functional access %s!\n",
365 accessSucceeded ? "successful":"failed");
366 }
367}
368
369void
370RubyPort::ruby_hit_callback(PacketPtr pkt)
371{
372 DPRINTF(RubyPort, "Hit callback for %s 0x%x\n", pkt->cmdString(),
373 pkt->getAddr());
374
375 // The packet was destined for memory and has not yet been turned
376 // into a response
377 assert(system->isMemAddr(pkt->getAddr()));
378 assert(pkt->isRequest());
379
380 // First we must retrieve the request port from the sender State
381 RubyPort::SenderState *senderState =
382 safe_cast<RubyPort::SenderState *>(pkt->popSenderState());
383 MemSlavePort *port = senderState->port;
384 assert(port != NULL);
385 delete senderState;
386
387 port->hitCallback(pkt);
388
389 trySendRetries();
390}
391
392void
393RubyPort::trySendRetries()
394{
395 //
396 // If we had to stall the MemSlavePorts, wake them up because the sequencer
397 // likely has free resources now.
398 //
399 if (!retryList.empty()) {
400 // Record the current list of ports to retry on a temporary list
401 // before calling sendRetryReq on those ports. sendRetryReq will cause
402 // an immediate retry, which may result in the ports being put back on
403 // the list. Therefore we want to clear the retryList before calling
404 // sendRetryReq.
405 std::vector<MemSlavePort *> curRetryList(retryList);
406
407 retryList.clear();
408
409 for (auto i = curRetryList.begin(); i != curRetryList.end(); ++i) {
410 DPRINTF(RubyPort,
411 "Sequencer may now be free. SendRetry to port %s\n",
412 (*i)->name());
413 (*i)->sendRetryReq();
414 }
415 }
416}
417
418void
419RubyPort::testDrainComplete()
420{
421 //If we weren't able to drain before, we might be able to now.
422 if (drainState() == DrainState::Draining) {
423 unsigned int drainCount = outstandingCount();
424 DPRINTF(Drain, "Drain count: %u\n", drainCount);
425 if (drainCount == 0) {
426 DPRINTF(Drain, "RubyPort done draining, signaling drain done\n");
427 signalDrainDone();
428 }
429 }
430}
431
432DrainState
433RubyPort::drain()
434{
435 if (isDeadlockEventScheduled()) {
436 descheduleDeadlockEvent();
437 }
438
439 //
440 // If the RubyPort is not empty, then it needs to clear all outstanding
441 // requests before it should call signalDrainDone()
442 //
443 DPRINTF(Config, "outstanding count %d\n", outstandingCount());
444 if (outstandingCount() > 0) {
445 DPRINTF(Drain, "RubyPort not drained\n");
446 return DrainState::Draining;
447 } else {
448 return DrainState::Drained;
449 }
450}
451
452void
453RubyPort::MemSlavePort::hitCallback(PacketPtr pkt)
454{
455 bool needsResponse = pkt->needsResponse();
456
457 // Unless specified at configuraiton, all responses except failed SC
458 // and Flush operations access M5 physical memory.
459 bool accessPhysMem = access_backing_store;
460
461 if (pkt->isLLSC()) {
462 if (pkt->isWrite()) {
463 if (pkt->req->getExtraData() != 0) {
464 //
465 // Successful SC packets convert to normal writes
466 //
467 pkt->convertScToWrite();
468 } else {
469 //
470 // Failed SC packets don't access physical memory and thus
471 // the RubyPort itself must convert it to a response.
472 //
473 accessPhysMem = false;
474 }
475 } else {
476 //
477 // All LL packets convert to normal loads so that M5 PhysMem does
478 // not lock the blocks.
479 //
480 pkt->convertLlToRead();
481 }
482 }
483
484 // Flush, acquire, release requests don't access physical memory
485 if (pkt->isFlush() || pkt->cmd == MemCmd::MemFenceReq) {
486 accessPhysMem = false;
487 }
488
489 if (pkt->req->isKernel()) {
490 accessPhysMem = false;
491 needsResponse = true;
492 }
493
494 DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse);
495
496 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
497 RubySystem *rs = ruby_port->m_ruby_system;
498 if (accessPhysMem) {
499 rs->getPhysMem()->access(pkt);
500 } else if (needsResponse) {
501 pkt->makeResponse();
502 }
503
504 // turn packet around to go back to requester if response expected
505 if (needsResponse) {
506 DPRINTF(RubyPort, "Sending packet back over port\n");
507 // Send a response in the same cycle. There is no need to delay the
508 // response because the response latency is already incurred in the
509 // Ruby protocol.
510 schedTimingResp(pkt, curTick());
511 } else {
512 delete pkt;
513 }
514
515 DPRINTF(RubyPort, "Hit callback done!\n");
516}
517
518AddrRangeList
519RubyPort::PioSlavePort::getAddrRanges() const
520{
521 // at the moment the assumption is that the master does not care
522 AddrRangeList ranges;
523 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
524
525 for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) {
526 ranges.splice(ranges.begin(),
527 ruby_port->master_ports[i]->getAddrRanges());
528 }
529 for (const auto M5_VAR_USED &r : ranges)
530 DPRINTF(RubyPort, "%s\n", r.to_string());
531 return ranges;
532}
533
534bool
535RubyPort::MemSlavePort::isPhysMemAddress(Addr addr) const
536{
537 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
538 return ruby_port->system->isMemAddr(addr);
539}
540
541void
542RubyPort::ruby_eviction_callback(Addr address)
543{
544 DPRINTF(RubyPort, "Sending invalidations.\n");
545 // Allocate the invalidate request and packet on the stack, as it is
546 // assumed they will not be modified or deleted by receivers.
547 // TODO: should this really be using funcMasterId?
548 Request request(address, RubySystem::getBlockSizeBytes(), 0,
549 Request::funcMasterId);
550 // Use a single packet to signal all snooping ports of the invalidation.
551 // This assumes that snooping ports do NOT modify the packet/request
552 Packet pkt(&request, MemCmd::InvalidateReq);
553 for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) {
554 // check if the connected master port is snooping
555 if ((*p)->isSnooping()) {
556 // send as a snoop request
557 (*p)->sendTimingSnoopReq(&pkt);
558 }
559 }
560}
561
562void
563RubyPort::PioMasterPort::recvRangeChange()
564{
565 RubyPort &r = static_cast<RubyPort &>(owner);
566 r.gotAddrRanges--;
567 if (r.gotAddrRanges == 0 && FullSystem) {
568 r.pioSlavePort.sendRangeChange();
569 }
570}