1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009 Advanced Micro Devices, Inc.
15 * Copyright (c) 2011 Mark D. Hill and David A. Wood
16 * All rights reserved.
17 *
18 * Redistribution and use in source and binary forms, with or without
19 * modification, are permitted provided that the following conditions are
20 * met: redistributions of source code must retain the above copyright
21 * notice, this list of conditions and the following disclaimer;
22 * redistributions in binary form must reproduce the above copyright
23 * notice, this list of conditions and the following disclaimer in the
24 * documentation and/or other materials provided with the distribution;
25 * neither the name of the copyright holders nor the names of its
26 * contributors may be used to endorse or promote products derived from
27 * this software without specific prior written permission.
28 *
29 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40 */
41
42#include "cpu/testers/rubytest/RubyTester.hh"
43#include "debug/Config.hh"
44#include "debug/Drain.hh"
45#include "debug/Ruby.hh"
46#include "mem/protocol/AccessPermission.hh"
47#include "mem/ruby/slicc_interface/AbstractController.hh"
48#include "mem/ruby/system/RubyPort.hh"
49#include "mem/simple_mem.hh"
50#include "sim/full_system.hh"
51#include "sim/system.hh"
52
53RubyPort::RubyPort(const Params *p)
54 : MemObject(p), m_ruby_system(p->ruby_system), m_version(p->version),
55 m_controller(NULL), m_mandatory_q_ptr(NULL),
56 m_usingRubyTester(p->using_ruby_tester), system(p->system),
57 pioMasterPort(csprintf("%s.pio-master-port", name()), this),
58 pioSlavePort(csprintf("%s.pio-slave-port", name()), this),
59 memMasterPort(csprintf("%s.mem-master-port", name()), this),
60 memSlavePort(csprintf("%s-mem-slave-port", name()), this,
61 p->ruby_system->getAccessBackingStore(), -1),
62 gotAddrRanges(p->port_master_connection_count)
63{
64 assert(m_version != -1);
65
66 // create the slave ports based on the number of connected ports
67 for (size_t i = 0; i < p->port_slave_connection_count; ++i) {
68 slave_ports.push_back(new MemSlavePort(csprintf("%s.slave%d", name(),
69 i), this, p->ruby_system->getAccessBackingStore(), i));
70 }
71
72 // create the master ports based on the number of connected ports
73 for (size_t i = 0; i < p->port_master_connection_count; ++i) {
74 master_ports.push_back(new PioMasterPort(csprintf("%s.master%d",
75 name(), i), this));
76 }
77}
78
79void
80RubyPort::init()
81{
82 assert(m_controller != NULL);
83 m_mandatory_q_ptr = m_controller->getMandatoryQueue();
84 m_mandatory_q_ptr->setSender(this);
85}
86
87BaseMasterPort &
88RubyPort::getMasterPort(const std::string &if_name, PortID idx)
89{
90 if (if_name == "mem_master_port") {
91 return memMasterPort;
92 }
93
94 if (if_name == "pio_master_port") {
95 return pioMasterPort;
96 }
97
98 // used by the x86 CPUs to connect the interrupt PIO and interrupt slave
99 // port
100 if (if_name != "master") {
101 // pass it along to our super class
102 return MemObject::getMasterPort(if_name, idx);
103 } else {
104 if (idx >= static_cast<PortID>(master_ports.size())) {
105 panic("RubyPort::getMasterPort: unknown index %d\n", idx);
106 }
107
108 return *master_ports[idx];
109 }
110}
111
112BaseSlavePort &
113RubyPort::getSlavePort(const std::string &if_name, PortID idx)
114{
115 if (if_name == "mem_slave_port") {
116 return memSlavePort;
117 }
118
119 if (if_name == "pio_slave_port")
120 return pioSlavePort;
121
122 // used by the CPUs to connect the caches to the interconnect, and
123 // for the x86 case also the interrupt master
124 if (if_name != "slave") {
125 // pass it along to our super class
126 return MemObject::getSlavePort(if_name, idx);
127 } else {
128 if (idx >= static_cast<PortID>(slave_ports.size())) {
129 panic("RubyPort::getSlavePort: unknown index %d\n", idx);
130 }
131
132 return *slave_ports[idx];
133 }
134}
135
136RubyPort::PioMasterPort::PioMasterPort(const std::string &_name,
137 RubyPort *_port)
138 : QueuedMasterPort(_name, _port, reqQueue, snoopRespQueue),
139 reqQueue(*_port, *this), snoopRespQueue(*_port, *this)
140{
141 DPRINTF(RubyPort, "Created master pioport on sequencer %s\n", _name);
142}
143
144RubyPort::PioSlavePort::PioSlavePort(const std::string &_name,
145 RubyPort *_port)
146 : QueuedSlavePort(_name, _port, queue), queue(*_port, *this)
147{
148 DPRINTF(RubyPort, "Created slave pioport on sequencer %s\n", _name);
149}
150
151RubyPort::MemMasterPort::MemMasterPort(const std::string &_name,
152 RubyPort *_port)
153 : QueuedMasterPort(_name, _port, reqQueue, snoopRespQueue),
154 reqQueue(*_port, *this), snoopRespQueue(*_port, *this)
155{
156 DPRINTF(RubyPort, "Created master memport on ruby sequencer %s\n", _name);
157}
158
159RubyPort::MemSlavePort::MemSlavePort(const std::string &_name, RubyPort *_port,
160 bool _access_backing_store, PortID id)
161 : QueuedSlavePort(_name, _port, queue, id), queue(*_port, *this),
162 access_backing_store(_access_backing_store)
163{
164 DPRINTF(RubyPort, "Created slave memport on ruby sequencer %s\n", _name);
165}
166
167bool
168RubyPort::PioMasterPort::recvTimingResp(PacketPtr pkt)
169{
170 RubyPort *rp = static_cast<RubyPort *>(&owner);
171 DPRINTF(RubyPort, "Response for address: 0x%#x\n", pkt->getAddr());
172
173 // send next cycle
174 rp->pioSlavePort.schedTimingResp(
175 pkt, curTick() + rp->m_ruby_system->clockPeriod());
176 return true;
177}
178
179bool RubyPort::MemMasterPort::recvTimingResp(PacketPtr pkt)
180{
181 // got a response from a device
182 assert(pkt->isResponse());
183
184 // First we must retrieve the request port from the sender State
185 RubyPort::SenderState *senderState =
186 safe_cast<RubyPort::SenderState *>(pkt->popSenderState());
187 MemSlavePort *port = senderState->port;
188 assert(port != NULL);
189 delete senderState;
190
191 // In FS mode, ruby memory will receive pio responses from devices
192 // and it must forward these responses back to the particular CPU.
193 DPRINTF(RubyPort, "Pio response for address %#x, going to %s\n",
194 pkt->getAddr(), port->name());
195
196 // attempt to send the response in the next cycle
197 RubyPort *rp = static_cast<RubyPort *>(&owner);
198 port->schedTimingResp(pkt, curTick() + rp->m_ruby_system->clockPeriod());
199
200 return true;
201}
202
203bool
204RubyPort::PioSlavePort::recvTimingReq(PacketPtr pkt)
205{
206 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
207
208 for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) {
209 AddrRangeList l = ruby_port->master_ports[i]->getAddrRanges();
210 for (auto it = l.begin(); it != l.end(); ++it) {
211 if (it->contains(pkt->getAddr())) {
212 // generally it is not safe to assume success here as
213 // the port could be blocked
214 bool M5_VAR_USED success =
215 ruby_port->master_ports[i]->sendTimingReq(pkt);
216 assert(success);
217 return true;
218 }
219 }
220 }
221 panic("Should never reach here!\n");
222}
223
224bool
225RubyPort::MemSlavePort::recvTimingReq(PacketPtr pkt)
226{
227 DPRINTF(RubyPort, "Timing request for address %#x on port %d\n",
228 pkt->getAddr(), id);
229 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
230
231 if (pkt->memInhibitAsserted())
232 panic("RubyPort should never see an inhibited request\n");
233
234 // Check for pio requests and directly send them to the dedicated
235 // pio port.
236 if (!isPhysMemAddress(pkt->getAddr())) {
237 assert(ruby_port->memMasterPort.isConnected());
238 DPRINTF(RubyPort, "Request address %#x assumed to be a pio address\n",
239 pkt->getAddr());
240
241 // Save the port in the sender state object to be used later to
242 // route the response
243 pkt->pushSenderState(new SenderState(this));
244
245 // send next cycle
246 RubySystem *rs = ruby_port->m_ruby_system;
247 ruby_port->memMasterPort.schedTimingReq(pkt,
248 curTick() + rs->clockPeriod());
249 return true;
250 }
251
252 assert(getOffset(pkt->getAddr()) + pkt->getSize() <=
253 RubySystem::getBlockSizeBytes());
254
255 // Submit the ruby request
256 RequestStatus requestStatus = ruby_port->makeRequest(pkt);
257
258 // If the request successfully issued then we should return true.
259 // Otherwise, we need to tell the port to retry at a later point
260 // and return false.
261 if (requestStatus == RequestStatus_Issued) {
262 // Save the port in the sender state object to be used later to
263 // route the response
264 pkt->pushSenderState(new SenderState(this));
265
266 DPRINTF(RubyPort, "Request %s 0x%x issued\n", pkt->cmdString(),
267 pkt->getAddr());
268 return true;
269 }
270
271 //
272 // Unless one is using the ruby tester, record the stalled M5 port for
273 // later retry when the sequencer becomes free.
274 //
275 if (!ruby_port->m_usingRubyTester) {
276 ruby_port->addToRetryList(this);
277 }
278
279 DPRINTF(RubyPort, "Request for address %#x did not issued because %s\n",
280 pkt->getAddr(), RequestStatus_to_string(requestStatus));
281
282 return false;
283}
284
285void
286RubyPort::MemSlavePort::recvFunctional(PacketPtr pkt)
287{
288 DPRINTF(RubyPort, "Functional access for address: %#x\n", pkt->getAddr());
289
290 RubyPort *rp M5_VAR_USED = static_cast<RubyPort *>(&owner);
291 RubySystem *rs = rp->m_ruby_system;
292
293 // Check for pio requests and directly send them to the dedicated
294 // pio port.
295 if (!isPhysMemAddress(pkt->getAddr())) {
296 assert(rp->memMasterPort.isConnected());
297 DPRINTF(RubyPort, "Pio Request for address: 0x%#x\n", pkt->getAddr());
298 panic("RubyPort::PioMasterPort::recvFunctional() not implemented!\n");
299 }
300
301 assert(pkt->getAddr() + pkt->getSize() <=
302 makeLineAddress(pkt->getAddr()) + RubySystem::getBlockSizeBytes());
303
304 if (access_backing_store) {
305 // The attached physmem contains the official version of data.
306 // The following command performs the real functional access.
307 // This line should be removed once Ruby supplies the official version
308 // of data.
309 rs->getPhysMem()->functionalAccess(pkt);
310 } else {
311 bool accessSucceeded = false;
312 bool needsResponse = pkt->needsResponse();
313
314 // Do the functional access on ruby memory
315 if (pkt->isRead()) {
316 accessSucceeded = rs->functionalRead(pkt);
317 } else if (pkt->isWrite()) {
318 accessSucceeded = rs->functionalWrite(pkt);
319 } else {
320 panic("Unsupported functional command %s\n", pkt->cmdString());
321 }
322
323 // Unless the requester explicitly said otherwise, generate an error if
324 // the functional request failed
325 if (!accessSucceeded && !pkt->suppressFuncError()) {
326 fatal("Ruby functional %s failed for address %#x\n",
327 pkt->isWrite() ? "write" : "read", pkt->getAddr());
328 }
329
330 // turn packet around to go back to requester if response expected
331 if (needsResponse) {
332 pkt->setFunctionalResponseStatus(accessSucceeded);
333 }
334
335 DPRINTF(RubyPort, "Functional access %s!\n",
336 accessSucceeded ? "successful":"failed");
337 }
338}
339
340void
341RubyPort::ruby_hit_callback(PacketPtr pkt)
342{
343 DPRINTF(RubyPort, "Hit callback for %s 0x%x\n", pkt->cmdString(),
344 pkt->getAddr());
345
346 // The packet was destined for memory and has not yet been turned
347 // into a response
348 assert(system->isMemAddr(pkt->getAddr()));
349 assert(pkt->isRequest());
350
351 // First we must retrieve the request port from the sender State
352 RubyPort::SenderState *senderState =
353 safe_cast<RubyPort::SenderState *>(pkt->popSenderState());
354 MemSlavePort *port = senderState->port;
355 assert(port != NULL);
356 delete senderState;
357
358 port->hitCallback(pkt);
359
360 //
361 // If we had to stall the MemSlavePorts, wake them up because the sequencer
362 // likely has free resources now.
363 //
364 if (!retryList.empty()) {
365 //
366 // Record the current list of ports to retry on a temporary list before
367 // calling sendRetry on those ports. sendRetry will cause an
368 // immediate retry, which may result in the ports being put back on the
369 // list. Therefore we want to clear the retryList before calling
370 // sendRetry.
371 //
372 std::vector<MemSlavePort *> curRetryList(retryList);
373
374 retryList.clear();
375
376 for (auto i = curRetryList.begin(); i != curRetryList.end(); ++i) {
377 DPRINTF(RubyPort,
378 "Sequencer may now be free. SendRetry to port %s\n",
379 (*i)->name());
380 (*i)->sendRetryReq();
381 }
382 }
383
384 testDrainComplete();
385}
386
387void
388RubyPort::testDrainComplete()
389{
390 //If we weren't able to drain before, we might be able to now.
391 if (drainState() == DrainState::Draining) {
392 unsigned int drainCount = outstandingCount();
393 DPRINTF(Drain, "Drain count: %u\n", drainCount);
394 if (drainCount == 0) {
395 DPRINTF(Drain, "RubyPort done draining, signaling drain done\n");
396 signalDrainDone();
397 }
398 }
399}
400
401DrainState
402RubyPort::drain()
403{
404 if (isDeadlockEventScheduled()) {
405 descheduleDeadlockEvent();
406 }
407
408 //
409 // If the RubyPort is not empty, then it needs to clear all outstanding
410 // requests before it should call signalDrainDone()
411 //
412 DPRINTF(Config, "outstanding count %d\n", outstandingCount());
413 if (outstandingCount() > 0) {
414 DPRINTF(Drain, "RubyPort not drained\n");
415 return DrainState::Draining;
416 } else {
417 return DrainState::Drained;
418 }
419}
420
421void
422RubyPort::MemSlavePort::hitCallback(PacketPtr pkt)
423{
424 bool needsResponse = pkt->needsResponse();
425
426 // Unless specified at configuraiton, all responses except failed SC
427 // and Flush operations access M5 physical memory.
428 bool accessPhysMem = access_backing_store;
429
430 if (pkt->isLLSC()) {
431 if (pkt->isWrite()) {
432 if (pkt->req->getExtraData() != 0) {
433 //
434 // Successful SC packets convert to normal writes
435 //
436 pkt->convertScToWrite();
437 } else {
438 //
439 // Failed SC packets don't access physical memory and thus
440 // the RubyPort itself must convert it to a response.
441 //
442 accessPhysMem = false;
443 }
444 } else {
445 //
446 // All LL packets convert to normal loads so that M5 PhysMem does
447 // not lock the blocks.
448 //
449 pkt->convertLlToRead();
450 }
451 }
452
453 // Flush requests don't access physical memory
454 if (pkt->isFlush()) {
455 accessPhysMem = false;
456 }
457
458 DPRINTF(RubyPort, "Hit callback needs response %d\n", needsResponse);
459
460 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
461 RubySystem *rs = ruby_port->m_ruby_system;
462 if (accessPhysMem) {
463 rs->getPhysMem()->access(pkt);
464 } else if (needsResponse) {
465 pkt->makeResponse();
466 }
467
468 // turn packet around to go back to requester if response expected
469 if (needsResponse) {
470 DPRINTF(RubyPort, "Sending packet back over port\n");
471 // Send a response in the same cycle. There is no need to delay the
472 // response because the response latency is already incurred in the
473 // Ruby protocol.
474 schedTimingResp(pkt, curTick());
475 } else {
476 delete pkt;
477 }
478
479 DPRINTF(RubyPort, "Hit callback done!\n");
480}
481
482AddrRangeList
483RubyPort::PioSlavePort::getAddrRanges() const
484{
485 // at the moment the assumption is that the master does not care
486 AddrRangeList ranges;
487 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
488
489 for (size_t i = 0; i < ruby_port->master_ports.size(); ++i) {
490 ranges.splice(ranges.begin(),
491 ruby_port->master_ports[i]->getAddrRanges());
492 }
493 for (const auto M5_VAR_USED &r : ranges)
494 DPRINTF(RubyPort, "%s\n", r.to_string());
495 return ranges;
496}
497
498bool
499RubyPort::MemSlavePort::isPhysMemAddress(Addr addr) const
500{
501 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
502 return ruby_port->system->isMemAddr(addr);
503}
504
505void
506RubyPort::ruby_eviction_callback(Addr address)
507{
508 DPRINTF(RubyPort, "Sending invalidations.\n");
509 // This request is deleted in the stack-allocated packet destructor
510 // when this function exits
511 // TODO: should this really be using funcMasterId?
512 RequestPtr req = new Request(address, 0, 0, Request::funcMasterId);
513 // Use a single packet to signal all snooping ports of the invalidation.
514 // This assumes that snooping ports do NOT modify the packet/request
515 Packet pkt(req, MemCmd::InvalidateReq);
516 for (CpuPortIter p = slave_ports.begin(); p != slave_ports.end(); ++p) {
517 // check if the connected master port is snooping
518 if ((*p)->isSnooping()) {
519 // send as a snoop request
520 (*p)->sendTimingSnoopReq(&pkt);
521 }
522 }
523}
524
525void
526RubyPort::PioMasterPort::recvRangeChange()
527{
528 RubyPort &r = static_cast<RubyPort &>(owner);
529 r.gotAddrRanges--;
530 if (r.gotAddrRanges == 0 && FullSystem) {
531 r.pioSlavePort.sendRangeChange();
532 }
533}