1/*
2 * Copyright (c) 2009 Advanced Micro Devices, Inc.
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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295
296bool
297RubyPort::M5Port::doFunctionalRead(PacketPtr pkt)
298{
299 Address address(pkt->getAddr());
300 Address line_address(address);
301 line_address.makeLineAddress();
302
303 AccessPermission accessPerm = AccessPermission_NotPresent;
304 int num_controllers = ruby_system->m_abs_cntrl_vec.size();
305
306 // In this loop, we try to figure which controller has a read only or
307 // a read write copy of the given address. Any valid copy would suffice
308 // for a functional read.
309
310 DPRINTF(RubyPort, "Functional Read request for %s\n",address);
311 for(int i = 0;i < num_controllers;++i)
312 {
313 accessPerm = ruby_system->m_abs_cntrl_vec[i]
314 ->getAccessPermission(line_address);
315 if(accessPerm == AccessPermission_Read_Only ||
316 accessPerm == AccessPermission_Read_Write)
317 {
318 unsigned startByte = address.getAddress() - line_address.getAddress();
319
320 uint8* data = pkt->getPtr<uint8_t>(true);
321 unsigned int size_in_bytes = pkt->getSize();
322 DataBlock& block = ruby_system->m_abs_cntrl_vec[i]
323 ->getDataBlock(line_address);
324
325 DPRINTF(RubyPort, "reading from %s block %s\n",
326 ruby_system->m_abs_cntrl_vec[i]->name(), block);
327 for (unsigned i = 0; i < size_in_bytes; ++i)
328 {
329 data[i] = block.getByte(i + startByte);
330 }
331 return true;
332 }
333 }
334 return false;
335}
336
337bool
338RubyPort::M5Port::doFunctionalWrite(PacketPtr pkt)
339{
340 Address addr(pkt->getAddr());
341 Address line_addr = line_address(addr);
342 AccessPermission accessPerm = AccessPermission_NotPresent;
343 int num_controllers = ruby_system->m_abs_cntrl_vec.size();
344
345 DPRINTF(RubyPort, "Functional Write request for %s\n",addr);
346
347 unsigned int num_ro = 0;
348 unsigned int num_rw = 0;
349 unsigned int num_busy = 0;
350
351 // In this loop we count the number of controllers that have the given
352 // address in read only, read write and busy states.
353 for(int i = 0;i < num_controllers;++i)
354 {
355 accessPerm = ruby_system->m_abs_cntrl_vec[i]->
356 getAccessPermission(line_addr);
357 if(accessPerm == AccessPermission_Read_Only) num_ro++;
358 else if(accessPerm == AccessPermission_Read_Write) num_rw++;
359 else if(accessPerm == AccessPermission_Busy) num_busy++;
360 }
361
362 // If the number of read write copies is more than 1, then there is bug in
363 // coherence protocol. Otherwise, if all copies are in stable states, i.e.
364 // num_busy == 0, we update all the copies. If there is at least one copy
365 // in busy state, then we check if there is read write copy. If yes, then
366 // also we let the access go through.
367
368 DPRINTF(RubyPort, "num_busy = %d, num_ro = %d, num_rw = %d\n",
369 num_busy, num_ro, num_rw);
370 assert(num_rw <= 1);
371 if((num_busy == 0 && num_ro > 0) || num_rw == 1)
372 {
373 uint8* data = pkt->getPtr<uint8_t>(true);
374 unsigned int size_in_bytes = pkt->getSize();
375 unsigned startByte = addr.getAddress() - line_addr.getAddress();
376
377 for(int i = 0; i < num_controllers;++i)
378 {
379 accessPerm = ruby_system->m_abs_cntrl_vec[i]->
380 getAccessPermission(line_addr);
381 if(accessPerm == AccessPermission_Read_Only ||
382 accessPerm == AccessPermission_Read_Write||
383 accessPerm == AccessPermission_Maybe_Stale)
384 {
385 DataBlock& block = ruby_system->m_abs_cntrl_vec[i]
386 ->getDataBlock(line_addr);
387
388 DPRINTF(RubyPort, "%s\n",block);
389 for (unsigned i = 0; i < size_in_bytes; ++i)
390 {
391 block.setByte(i + startByte, data[i]);
392 }
393 DPRINTF(RubyPort, "%s\n",block);
394 }
395 }
396 return true;
397 }
398 return false;

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