1/*
2 * Copyright (c) 2012-2013 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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221 assert(success);
222 return true;
223 }
224 }
225 }
226 panic("Should never reach here!\n");
227}
228
229bool
230RubyPort::MemSlavePort::recvTimingReq(PacketPtr pkt)
231{
232 DPRINTF(RubyPort, "Timing request for address %#x on port %d\n",
233 pkt->getAddr(), id);
234 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
235
236 if (pkt->cacheResponding())

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290 pkt->getAddr(), RequestStatus_to_string(requestStatus));
291 }
292
293 addToRetryList();
294
295 return false;
296}
297
298void
299RubyPort::MemSlavePort::addToRetryList()
300{
301 RubyPort *ruby_port = static_cast<RubyPort *>(&owner);
302
303 //
304 // Unless the requestor do not want retries (e.g., the Ruby tester),
305 // record the stalled M5 port for later retry when the sequencer

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