AbstractController.hh (9363:e2616dc035ce) AbstractController.hh (9364:e5fc9d588132)
1/*
2 * Copyright (c) 2009 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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27 */
28
29#ifndef __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
30#define __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
31
32#include <iostream>
33#include <string>
34
1/*
2 * Copyright (c) 2009 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 18 unchanged lines hidden (view full) ---

27 */
28
29#ifndef __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
30#define __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
31
32#include <iostream>
33#include <string>
34
35#include "mem/packet.hh"
36#include "mem/protocol/AccessPermission.hh"
37#include "mem/ruby/common/Address.hh"
38#include "mem/ruby/common/Consumer.hh"
39#include "mem/ruby/common/DataBlock.hh"
40#include "mem/ruby/network/Network.hh"
41#include "mem/ruby/recorder/CacheRecorder.hh"
35#include "mem/protocol/AccessPermission.hh"
36#include "mem/ruby/common/Address.hh"
37#include "mem/ruby/common/Consumer.hh"
38#include "mem/ruby/common/DataBlock.hh"
39#include "mem/ruby/network/Network.hh"
40#include "mem/ruby/recorder/CacheRecorder.hh"
41#include "mem/ruby/system/MachineID.hh"
42#include "mem/packet.hh"
42#include "params/RubyController.hh"
43#include "sim/sim_object.hh"
44
45class MessageBuffer;
46class Network;
47
48class AbstractController : public SimObject, public Consumer
49{

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77 virtual bool functionalReadBuffers(PacketPtr&) = 0;
78 //! The return value indicates the number of messages written with the
79 //! data from the packet.
80 virtual uint32_t functionalWriteBuffers(PacketPtr&) = 0;
81
82 //! Function for enqueuing a prefetch request
83 virtual void enqueuePrefetch(const Address&, const RubyRequestType&)
84 { fatal("Prefetches not implemented!");}
43#include "params/RubyController.hh"
44#include "sim/sim_object.hh"
45
46class MessageBuffer;
47class Network;
48
49class AbstractController : public SimObject, public Consumer
50{

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78 virtual bool functionalReadBuffers(PacketPtr&) = 0;
79 //! The return value indicates the number of messages written with the
80 //! data from the packet.
81 virtual uint32_t functionalWriteBuffers(PacketPtr&) = 0;
82
83 //! Function for enqueuing a prefetch request
84 virtual void enqueuePrefetch(const Address&, const RubyRequestType&)
85 { fatal("Prefetches not implemented!");}
86
87 protected:
88 int m_transitions_per_cycle;
89 int m_buffer_size;
90 int m_recycle_latency;
91 std::string m_name;
92 std::map<std::string, std::string> m_cfg;
93 NodeID m_version;
94 Network* m_net_ptr;
95 MachineID m_machineID;
96 bool m_is_blocking;
97 std::map<Address, MessageBuffer*> m_block_map;
98 typedef std::vector<MessageBuffer*> MsgVecType;
99 typedef std::map< Address, MsgVecType* > WaitingBufType;
100 WaitingBufType m_waiting_buffers;
101 int m_max_in_port_rank;
102 int m_cur_in_port_rank;
103 int m_number_of_TBEs;
85};
86
87#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
104};
105
106#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__