AbstractController.hh (9117:49116b947194) | AbstractController.hh (9302:c2e70a9bc340) |
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1/* 2 * Copyright (c) 2009 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 18 unchanged lines hidden (view full) --- 27 */ 28 29#ifndef __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__ 30#define __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__ 31 32#include <iostream> 33#include <string> 34 | 1/* 2 * Copyright (c) 2009 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 18 unchanged lines hidden (view full) --- 27 */ 28 29#ifndef __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__ 30#define __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__ 31 32#include <iostream> 33#include <string> 34 |
35#include "mem/packet.hh" |
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35#include "mem/protocol/AccessPermission.hh" 36#include "mem/ruby/common/Address.hh" 37#include "mem/ruby/common/Consumer.hh" 38#include "mem/ruby/common/DataBlock.hh" 39#include "mem/ruby/network/Network.hh" 40#include "mem/ruby/recorder/CacheRecorder.hh" 41#include "params/RubyController.hh" 42#include "sim/sim_object.hh" --- 20 unchanged lines hidden (view full) --- 63 64 virtual void print(std::ostream & out) const = 0; 65 virtual void printStats(std::ostream & out) const = 0; 66 virtual void wakeup() = 0; 67 // virtual void dumpStats(std::ostream & out) = 0; 68 virtual void clearStats() = 0; 69 virtual void recordCacheTrace(int cntrl, CacheRecorder* tr) = 0; 70 virtual Sequencer* getSequencer() const = 0; | 36#include "mem/protocol/AccessPermission.hh" 37#include "mem/ruby/common/Address.hh" 38#include "mem/ruby/common/Consumer.hh" 39#include "mem/ruby/common/DataBlock.hh" 40#include "mem/ruby/network/Network.hh" 41#include "mem/ruby/recorder/CacheRecorder.hh" 42#include "params/RubyController.hh" 43#include "sim/sim_object.hh" --- 20 unchanged lines hidden (view full) --- 64 65 virtual void print(std::ostream & out) const = 0; 66 virtual void printStats(std::ostream & out) const = 0; 67 virtual void wakeup() = 0; 68 // virtual void dumpStats(std::ostream & out) = 0; 69 virtual void clearStats() = 0; 70 virtual void recordCacheTrace(int cntrl, CacheRecorder* tr) = 0; 71 virtual Sequencer* getSequencer() const = 0; |
72 73 //! These functions are used by ruby system to read/write the message 74 //! queues that exist with in the controller. 75 //! The boolean return value indicates if the read was performed 76 //! successfully. 77 virtual bool functionalReadBuffers(PacketPtr&) = 0; 78 //! The return value indicates the number of messages written with the 79 //! data from the packet. 80 virtual uint32_t functionalWriteBuffers(PacketPtr&) = 0; |
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71}; 72 73#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__ | 81}; 82 83#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__ |