AbstractController.hh (13784:1941dc118243) AbstractController.hh (13892:0182a0601f66)
1/*
2 * Copyright (c) 2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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42#define __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
43
44#include <exception>
45#include <iostream>
46#include <string>
47
48#include "base/addr_range.hh"
49#include "base/callback.hh"
1/*
2 * Copyright (c) 2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

--- 33 unchanged lines hidden (view full) ---

42#define __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
43
44#include <exception>
45#include <iostream>
46#include <string>
47
48#include "base/addr_range.hh"
49#include "base/callback.hh"
50#include "mem/mem_object.hh"
51#include "mem/packet.hh"
52#include "mem/protocol/AccessPermission.hh"
53#include "mem/qport.hh"
54#include "mem/ruby/common/Address.hh"
55#include "mem/ruby/common/Consumer.hh"
56#include "mem/ruby/common/DataBlock.hh"
57#include "mem/ruby/common/Histogram.hh"
58#include "mem/ruby/common/MachineID.hh"
59#include "mem/ruby/network/MessageBuffer.hh"
60#include "mem/ruby/system/CacheRecorder.hh"
61#include "params/RubyController.hh"
50#include "mem/packet.hh"
51#include "mem/protocol/AccessPermission.hh"
52#include "mem/qport.hh"
53#include "mem/ruby/common/Address.hh"
54#include "mem/ruby/common/Consumer.hh"
55#include "mem/ruby/common/DataBlock.hh"
56#include "mem/ruby/common/Histogram.hh"
57#include "mem/ruby/common/MachineID.hh"
58#include "mem/ruby/network/MessageBuffer.hh"
59#include "mem/ruby/system/CacheRecorder.hh"
60#include "params/RubyController.hh"
61#include "sim/clocked_object.hh"
62
63class Network;
64class GPUCoalescer;
65
66// used to communicate that an in_port peeked the wrong message type
67class RejectException: public std::exception
68{
69 virtual const char* what() const throw()
70 { return "Port rejected message based on type"; }
71};
72
62
63class Network;
64class GPUCoalescer;
65
66// used to communicate that an in_port peeked the wrong message type
67class RejectException: public std::exception
68{
69 virtual const char* what() const throw()
70 { return "Port rejected message based on type"; }
71};
72
73class AbstractController : public MemObject, public Consumer
73class AbstractController : public ClockedObject, public Consumer
74{
75 public:
76 typedef RubyControllerParams Params;
77 AbstractController(const Params *p);
78 void init();
79 const Params *params() const { return (const Params *)_params; }
80
81 NodeID getVersion() const { return m_machineID.getNum(); }

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75 public:
76 typedef RubyControllerParams Params;
77 AbstractController(const Params *p);
78 void init();
79 const Params *params() const { return (const Params *)_params; }
80
81 NodeID getVersion() const { return m_machineID.getNum(); }

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