AbstractController.hh (10977:9b3b9be42dd9) | AbstractController.hh (11021:e8a6637afa4c) |
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1/* 2 * Copyright (c) 2009-2014 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 61 unchanged lines hidden (view full) --- 70 71 void initNetworkPtr(Network* net_ptr) { m_net_ptr = net_ptr; } 72 73 // return instance name 74 void blockOnQueue(Address, MessageBuffer*); 75 void unblock(Address); 76 77 virtual MessageBuffer* getMandatoryQueue() const = 0; | 1/* 2 * Copyright (c) 2009-2014 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 61 unchanged lines hidden (view full) --- 70 71 void initNetworkPtr(Network* net_ptr) { m_net_ptr = net_ptr; } 72 73 // return instance name 74 void blockOnQueue(Address, MessageBuffer*); 75 void unblock(Address); 76 77 virtual MessageBuffer* getMandatoryQueue() const = 0; |
78 virtual MessageBuffer* getMemoryQueue() const = 0; |
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78 virtual AccessPermission getAccessPermission(const Address& addr) = 0; 79 80 virtual void print(std::ostream & out) const = 0; 81 virtual void wakeup() = 0; 82 virtual void resetStats() = 0; 83 virtual void regStats(); 84 85 virtual void recordCacheTrace(int cntrl, CacheRecorder* tr) = 0; --- 14 unchanged lines hidden (view full) --- 100 { fatal("Prefetches not implemented!");} 101 102 //! Function for collating statistics from all the controllers of this 103 //! particular type. This function should only be called from the 104 //! version 0 of this controller type. 105 virtual void collateStats() 106 {fatal("collateStats() should be overridden!");} 107 | 79 virtual AccessPermission getAccessPermission(const Address& addr) = 0; 80 81 virtual void print(std::ostream & out) const = 0; 82 virtual void wakeup() = 0; 83 virtual void resetStats() = 0; 84 virtual void regStats(); 85 86 virtual void recordCacheTrace(int cntrl, CacheRecorder* tr) = 0; --- 14 unchanged lines hidden (view full) --- 101 { fatal("Prefetches not implemented!");} 102 103 //! Function for collating statistics from all the controllers of this 104 //! particular type. This function should only be called from the 105 //! version 0 of this controller type. 106 virtual void collateStats() 107 {fatal("collateStats() should be overridden!");} 108 |
108 //! Set the message buffer with given name. 109 virtual void setNetQueue(const std::string& name, MessageBuffer *b) = 0; | 109 //! Initialize the message buffers. 110 virtual void initNetQueues() = 0; |
110 111 /** A function used to return the port associated with this bus object. */ 112 BaseMasterPort& getMasterPort(const std::string& if_name, 113 PortID idx = InvalidPortID); 114 115 void queueMemoryRead(const MachineID &id, Address addr, Cycles latency); 116 void queueMemoryWrite(const MachineID &id, Address addr, Cycles latency, 117 const DataBlock &block); --- 87 unchanged lines hidden (view full) --- 205 // Currently the pkt is handed to the coherence controller 206 // associated with this port. 207 bool recvTimingResp(PacketPtr pkt); 208 }; 209 210 /* Master port to the memory controller. */ 211 MemoryPort memoryPort; 212 | 111 112 /** A function used to return the port associated with this bus object. */ 113 BaseMasterPort& getMasterPort(const std::string& if_name, 114 PortID idx = InvalidPortID); 115 116 void queueMemoryRead(const MachineID &id, Address addr, Cycles latency); 117 void queueMemoryWrite(const MachineID &id, Address addr, Cycles latency, 118 const DataBlock &block); --- 87 unchanged lines hidden (view full) --- 206 // Currently the pkt is handed to the coherence controller 207 // associated with this port. 208 bool recvTimingResp(PacketPtr pkt); 209 }; 210 211 /* Master port to the memory controller. */ 212 MemoryPort memoryPort; 213 |
213 // Message Buffer for storing the response received from the 214 // memory controller. 215 MessageBuffer *m_responseFromMemory_ptr; 216 | |
217 // State that is stored in packets sent to the memory controller. 218 struct SenderState : public Packet::SenderState 219 { 220 // Id of the machine from which the request originated. 221 MachineID id; 222 223 SenderState(MachineID _id) : id(_id) 224 {} 225 }; 226}; 227 228#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__ | 214 // State that is stored in packets sent to the memory controller. 215 struct SenderState : public Packet::SenderState 216 { 217 // Id of the machine from which the request originated. 218 MachineID id; 219 220 SenderState(MachineID _id) : id(_id) 221 {} 222 }; 223}; 224 225#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__ |