AbstractController.hh (10523:5777a3e55603) AbstractController.hh (10524:fff17530cef6)
1/*
1/*
2 * Copyright (c) 2009 Mark D. Hill and David A. Wood
2 * Copyright (c) 2009-2014 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the

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38#include "mem/ruby/common/Consumer.hh"
39#include "mem/ruby/common/DataBlock.hh"
40#include "mem/ruby/common/Histogram.hh"
41#include "mem/ruby/common/MachineID.hh"
42#include "mem/ruby/network/MessageBuffer.hh"
43#include "mem/ruby/network/Network.hh"
44#include "mem/ruby/system/CacheRecorder.hh"
45#include "mem/packet.hh"
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the

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38#include "mem/ruby/common/Consumer.hh"
39#include "mem/ruby/common/DataBlock.hh"
40#include "mem/ruby/common/Histogram.hh"
41#include "mem/ruby/common/MachineID.hh"
42#include "mem/ruby/network/MessageBuffer.hh"
43#include "mem/ruby/network/Network.hh"
44#include "mem/ruby/system/CacheRecorder.hh"
45#include "mem/packet.hh"
46#include "mem/qport.hh"
46#include "params/RubyController.hh"
47#include "params/RubyController.hh"
47#include "sim/clocked_object.hh"
48#include "mem/mem_object.hh"
48
49class Network;
50
49
50class Network;
51
51class AbstractController : public ClockedObject, public Consumer
52class AbstractController : public MemObject, public Consumer
52{
53 public:
54 typedef RubyControllerParams Params;
55 AbstractController(const Params *p);
56 void init();
57 const Params *params() const { return (const Params *)_params; }
58
59 const NodeID getVersion() const { return m_machineID.getNum(); }

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74 virtual void regStats();
75
76 virtual void recordCacheTrace(int cntrl, CacheRecorder* tr) = 0;
77 virtual Sequencer* getSequencer() const = 0;
78
79 //! These functions are used by ruby system to read/write the data blocks
80 //! that exist with in the controller.
81 virtual void functionalRead(const Address &addr, PacketPtr) = 0;
53{
54 public:
55 typedef RubyControllerParams Params;
56 AbstractController(const Params *p);
57 void init();
58 const Params *params() const { return (const Params *)_params; }
59
60 const NodeID getVersion() const { return m_machineID.getNum(); }

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75 virtual void regStats();
76
77 virtual void recordCacheTrace(int cntrl, CacheRecorder* tr) = 0;
78 virtual Sequencer* getSequencer() const = 0;
79
80 //! These functions are used by ruby system to read/write the data blocks
81 //! that exist with in the controller.
82 virtual void functionalRead(const Address &addr, PacketPtr) = 0;
83 void functionalMemoryRead(PacketPtr);
82 //! The return value indicates the number of messages written with the
83 //! data from the packet.
84 //! The return value indicates the number of messages written with the
85 //! data from the packet.
84 virtual uint32_t functionalWriteBuffers(PacketPtr&) = 0;
86 virtual int functionalWriteBuffers(PacketPtr&) = 0;
85 virtual int functionalWrite(const Address &addr, PacketPtr) = 0;
87 virtual int functionalWrite(const Address &addr, PacketPtr) = 0;
88 int functionalMemoryWrite(PacketPtr);
86
87 //! Function for enqueuing a prefetch request
88 virtual void enqueuePrefetch(const Address&, const RubyRequestType&)
89 { fatal("Prefetches not implemented!");}
90
91 //! Function for collating statistics from all the controllers of this
92 //! particular type. This function should only be called from the
93 //! version 0 of this controller type.
94 virtual void collateStats()
95 {fatal("collateStats() should be overridden!");}
96
97 //! Set the message buffer with given name.
98 virtual void setNetQueue(const std::string& name, MessageBuffer *b) = 0;
99
89
90 //! Function for enqueuing a prefetch request
91 virtual void enqueuePrefetch(const Address&, const RubyRequestType&)
92 { fatal("Prefetches not implemented!");}
93
94 //! Function for collating statistics from all the controllers of this
95 //! particular type. This function should only be called from the
96 //! version 0 of this controller type.
97 virtual void collateStats()
98 {fatal("collateStats() should be overridden!");}
99
100 //! Set the message buffer with given name.
101 virtual void setNetQueue(const std::string& name, MessageBuffer *b) = 0;
102
103 /** A function used to return the port associated with this bus object. */
104 BaseMasterPort& getMasterPort(const std::string& if_name,
105 PortID idx = InvalidPortID);
106
107 void queueMemoryRead(const MachineID &id, Address addr, Cycles latency);
108 void queueMemoryWrite(const MachineID &id, Address addr, Cycles latency,
109 const DataBlock &block);
110 void queueMemoryWritePartial(const MachineID &id, Address addr, Cycles latency,
111 const DataBlock &block, int size);
112 void recvTimingResp(PacketPtr pkt);
113
100 public:
101 MachineID getMachineID() const { return m_machineID; }
102
103 Stats::Histogram& getDelayHist() { return m_delayHistogram; }
104 Stats::Histogram& getDelayVCHist(uint32_t index)
105 { return *(m_delayVCHistogram[index]); }
106
107 protected:

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115 void wakeUpAllBuffers(Address addr);
116 void wakeUpAllBuffers();
117
118 protected:
119 NodeID m_version;
120 MachineID m_machineID;
121 NodeID m_clusterID;
122
114 public:
115 MachineID getMachineID() const { return m_machineID; }
116
117 Stats::Histogram& getDelayHist() { return m_delayHistogram; }
118 Stats::Histogram& getDelayVCHist(uint32_t index)
119 { return *(m_delayVCHistogram[index]); }
120
121 protected:

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129 void wakeUpAllBuffers(Address addr);
130 void wakeUpAllBuffers();
131
132 protected:
133 NodeID m_version;
134 MachineID m_machineID;
135 NodeID m_clusterID;
136
137 // MasterID used by some components of gem5.
138 MasterID m_masterId;
139
123 Network* m_net_ptr;
124 bool m_is_blocking;
125 std::map<Address, MessageBuffer*> m_block_map;
126
127 typedef std::vector<MessageBuffer*> MsgVecType;
128 typedef std::map< Address, MsgVecType* > WaitingBufType;
129 WaitingBufType m_waiting_buffers;
130

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151 private:
152 AbstractController *ctr;
153
154 public:
155 virtual ~StatsCallback() {}
156 StatsCallback(AbstractController *_ctr) : ctr(_ctr) {}
157 void process() {ctr->collateStats();}
158 };
140 Network* m_net_ptr;
141 bool m_is_blocking;
142 std::map<Address, MessageBuffer*> m_block_map;
143
144 typedef std::vector<MessageBuffer*> MsgVecType;
145 typedef std::map< Address, MsgVecType* > WaitingBufType;
146 WaitingBufType m_waiting_buffers;
147

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168 private:
169 AbstractController *ctr;
170
171 public:
172 virtual ~StatsCallback() {}
173 StatsCallback(AbstractController *_ctr) : ctr(_ctr) {}
174 void process() {ctr->collateStats();}
175 };
176
177 /**
178 * Port that forwards requests and receives responses from the
179 * memory controller. It has a queue of packets not yet sent.
180 */
181 class MemoryPort : public QueuedMasterPort
182 {
183 private:
184 // Packet queue used to store outgoing requests and responses.
185 MasterPacketQueue _queue;
186
187 // Controller that operates this port.
188 AbstractController *controller;
189
190 public:
191 MemoryPort(const std::string &_name, AbstractController *_controller,
192 const std::string &_label);
193
194 // Function for receiving a timing response from the peer port.
195 // Currently the pkt is handed to the coherence controller
196 // associated with this port.
197 bool recvTimingResp(PacketPtr pkt);
198 };
199
200 /* Master port to the memory controller. */
201 MemoryPort memoryPort;
202
203 // Message Buffer for storing the response received from the
204 // memory controller.
205 MessageBuffer *m_responseFromMemory_ptr;
206
207 // State that is stored in packets sent to the memory controller.
208 struct SenderState : public Packet::SenderState
209 {
210 // Id of the machine from which the request originated.
211 MachineID id;
212
213 SenderState(MachineID _id) : id(_id)
214 {}
215 };
159};
160
161#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
216};
217
218#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__