1/* 2 * Copyright (c) 2009 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 19 unchanged lines hidden (view full) --- 28 29#ifndef __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__ 30#define __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__ 31 32#include <iostream> 33#include <string> 34 35#include "mem/protocol/AccessPermission.hh" |
36#include "mem/ruby/common/Address.hh" 37#include "mem/ruby/common/Consumer.hh" 38#include "mem/ruby/common/DataBlock.hh" 39#include "mem/ruby/network/Network.hh" |
40#include "mem/ruby/recorder/CacheRecorder.hh" |
41#include "params/RubyController.hh" 42#include "sim/sim_object.hh" 43 44class MessageBuffer; 45class Network; 46 47class AbstractController : public SimObject, public Consumer 48{ --- 13 unchanged lines hidden (view full) --- 62 virtual DataBlock& getDataBlock(const Address& addr) = 0; 63 64 virtual void print(std::ostream & out) const = 0; 65 virtual void printStats(std::ostream & out) const = 0; 66 virtual void printConfig(std::ostream & out) const = 0; 67 virtual void wakeup() = 0; 68 // virtual void dumpStats(std::ostream & out) = 0; 69 virtual void clearStats() = 0; |
70 virtual void recordCacheTrace(int cntrl, CacheRecorder* tr) = 0; 71 virtual Sequencer* getSequencer() const = 0; |
72}; 73 74#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__ |