1/* 2 * Copyright (c) 2017 ARM Limited 3 * All rights reserved. 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 121 unchanged lines hidden (view full) --- 130 PortID idx = InvalidPortID); 131 132 void queueMemoryRead(const MachineID &id, Addr addr, Cycles latency); 133 void queueMemoryWrite(const MachineID &id, Addr addr, Cycles latency, 134 const DataBlock &block); 135 void queueMemoryWritePartial(const MachineID &id, Addr addr, Cycles latency, 136 const DataBlock &block, int size); 137 void recvTimingResp(PacketPtr pkt); |
138 Tick recvAtomic(PacketPtr pkt); |
139 140 const AddrRangeList &getAddrRanges() const { return addrRanges; } 141 142 public: 143 MachineID getMachineID() const { return m_machineID; } 144 145 Stats::Histogram& getDelayHist() { return m_delayHistogram; } 146 Stats::Histogram& getDelayVCHist(uint32_t index) --- 117 unchanged lines hidden --- |