1/*
2 * Copyright (c) 2017 ARM Limited
3 * All rights reserved.
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2009-2014 Mark D. Hill and David A. Wood
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright

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40
41#ifndef __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
42#define __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
43
44#include <exception>
45#include <iostream>
46#include <string>
47
48#include "base/addr_range.hh"
49#include "base/callback.hh"
50#include "mem/mem_object.hh"
51#include "mem/packet.hh"
52#include "mem/protocol/AccessPermission.hh"
53#include "mem/qport.hh"
54#include "mem/ruby/common/Address.hh"
55#include "mem/ruby/common/Consumer.hh"
56#include "mem/ruby/common/DataBlock.hh"
57#include "mem/ruby/common/Histogram.hh"
58#include "mem/ruby/common/MachineID.hh"
59#include "mem/ruby/network/MessageBuffer.hh"
60#include "mem/ruby/system/CacheRecorder.hh"
45#include "mem/packet.hh"
46#include "mem/qport.hh"
61#include "params/RubyController.hh"
48#include "mem/mem_object.hh"
62
63class Network;
64class GPUCoalescer;
65
66// used to communicate that an in_port peeked the wrong message type
67class RejectException: public std::exception
68{
69 virtual const char* what() const throw()

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131
132 void queueMemoryRead(const MachineID &id, Addr addr, Cycles latency);
133 void queueMemoryWrite(const MachineID &id, Addr addr, Cycles latency,
134 const DataBlock &block);
135 void queueMemoryWritePartial(const MachineID &id, Addr addr, Cycles latency,
136 const DataBlock &block, int size);
137 void recvTimingResp(PacketPtr pkt);
138
139 const AddrRangeList &getAddrRanges() const { return addrRanges; }
140
141 public:
142 MachineID getMachineID() const { return m_machineID; }
143
144 Stats::Histogram& getDelayHist() { return m_delayHistogram; }
145 Stats::Histogram& getDelayVCHist(uint32_t index)
146 { return *(m_delayVCHistogram[index]); }
147
148 /**
149 * Map an address to the correct MachineID
150 *
151 * This function querries the network for the NodeID of the
152 * destination for a given request using its address and the type
153 * of the destination. For example for a request with a given
154 * address to a directory it will return the MachineID of the
155 * authorative directory.
156 *
157 * @param the destination address
158 * @param the type of the destination
159 * @return the MachineID of the destination
160 */
161 MachineID mapAddressToMachine(Addr addr, MachineType mtype) const;
162
163 protected:
164 //! Profiles original cache requests including PUTs
165 void profileRequest(const std::string &request);
166 //! Profiles the delay associated with messages.
167 void profileMsgDelay(uint32_t virtualNetwork, Cycles delay);
168
169 void stallBuffer(MessageBuffer* buf, Addr addr);
170 void wakeUpBuffers(Addr addr);

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248 struct SenderState : public Packet::SenderState
249 {
250 // Id of the machine from which the request originated.
251 MachineID id;
252
253 SenderState(MachineID _id) : id(_id)
254 {}
255 };
256
257 private:
258 /** The address range to which the controller responds on the CPU side. */
259 const AddrRangeList addrRanges;
260};
261
262#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__