1/*
2 * Copyright (c) 2009 Mark D. Hill and David A. Wood
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 18 unchanged lines hidden (view full) ---

27 */
28
29#ifndef __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
30#define __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__
31
32#include <iostream>
33#include <string>
34
35#include "mem/packet.hh"
36#include "mem/protocol/AccessPermission.hh"
37#include "mem/ruby/common/Address.hh"
38#include "mem/ruby/common/Consumer.hh"
39#include "mem/ruby/common/DataBlock.hh"
40#include "mem/ruby/network/Network.hh"
41#include "mem/ruby/recorder/CacheRecorder.hh"
42#include "params/RubyController.hh"
43#include "sim/sim_object.hh"
44
45class MessageBuffer;
46class Network;
47
48class AbstractController : public SimObject, public Consumer
49{

--- 27 unchanged lines hidden (view full) ---

77 virtual bool functionalReadBuffers(PacketPtr&) = 0;
78 //! The return value indicates the number of messages written with the
79 //! data from the packet.
80 virtual uint32_t functionalWriteBuffers(PacketPtr&) = 0;
81
82 //! Function for enqueuing a prefetch request
83 virtual void enqueuePrefetch(const Address&, const RubyRequestType&)
84 { fatal("Prefetches not implemented!");}
85};
86
87#endif // __MEM_RUBY_SLICC_INTERFACE_ABSTRACTCONTROLLER_HH__