1
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1/* 2 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; 9 * redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution; 12 * neither the name of the copyright holders nor the names of its 13 * contributors may be used to endorse or promote products derived from 14 * this software without specific prior written permission. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29/*
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31 * $Id$
32 *
33 * Description: Perfect switch, of course it is perfect and no latency or what
34 * so ever. Every cycle it is woke up and perform all the
35 * necessary routings that must be done. Note, this switch also
36 * has number of input ports/output ports and has a routing table
37 * as well.
38 *
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30 * Perfect switch, of course it is perfect and no latency or what so 31 * ever. Every cycle it is woke up and perform all the necessary 32 * routings that must be done. Note, this switch also has number of 33 * input ports/output ports and has a routing table as well. |
34 */ 35
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41#ifndef PerfectSwitch_H
42#define PerfectSwitch_H
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36#ifndef __MEM_RUBY_NETWORK_SIMPLE_PERFECTSWITCH_HH__ 37#define __MEM_RUBY_NETWORK_SIMPLE_PERFECTSWITCH_HH__ |
38 39#include <iostream> 40
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46#include "mem/ruby/common/Global.hh"
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41#include "mem/gems_common/Vector.hh" 42#include "mem/ruby/common/Consumer.hh"
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43#include "mem/ruby/common/Global.hh" |
44#include "mem/ruby/system/NodeID.hh" 45 46class MessageBuffer; 47class NetDest; 48class SimpleNetwork; 49
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55class LinkOrder {
56public:
57 int m_link;
58 int m_value;
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50struct LinkOrder 51{ 52 int m_link; 53 int m_value; |
54}; 55
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61class PerfectSwitch : public Consumer {
62public:
63 // Constructors
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56class PerfectSwitch : public Consumer 57{ 58 public: 59 PerfectSwitch(SwitchID sid, SimpleNetwork* network_ptr); 60 ~PerfectSwitch(); |
61
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65 // constructor specifying the number of ports
66 PerfectSwitch(SwitchID sid, SimpleNetwork* network_ptr);
67 void addInPort(const Vector<MessageBuffer*>& in);
68 void addOutPort(const Vector<MessageBuffer*>& out, const NetDest& routing_table_entry);
69 void clearRoutingTables();
70 void clearBuffers();
71 void reconfigureOutPort(const NetDest& routing_table_entry);
72 int getInLinks() const { return m_in.size(); }
73 int getOutLinks() const { return m_out.size(); }
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62 void addInPort(const Vector<MessageBuffer*>& in); 63 void addOutPort(const Vector<MessageBuffer*>& out, 64 const NetDest& routing_table_entry); 65 void clearRoutingTables(); 66 void clearBuffers(); 67 void reconfigureOutPort(const NetDest& routing_table_entry); 68 int getInLinks() const { return m_in.size(); } 69 int getOutLinks() const { return m_out.size(); } |
70
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75 // Destructor
76 ~PerfectSwitch();
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71 void wakeup(); |
72
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78 // Public Methods
79 void wakeup();
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73 void printStats(std::ostream& out) const; 74 void clearStats(); 75 void printConfig(std::ostream& out) const; |
76
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81 void printStats(std::ostream& out) const;
82 void clearStats();
83 void printConfig(std::ostream& out) const;
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77 void print(std::ostream& out) const; |
78
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85 void print(std::ostream& out) const;
86private:
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79 private: 80 // Private copy constructor and assignment operator 81 PerfectSwitch(const PerfectSwitch& obj); 82 PerfectSwitch& operator=(const PerfectSwitch& obj); |
83
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88 // Private copy constructor and assignment operator
89 PerfectSwitch(const PerfectSwitch& obj);
90 PerfectSwitch& operator=(const PerfectSwitch& obj);
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84 SwitchID m_switch_id; |
85
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92 // Data Members (m_ prefix)
93 SwitchID m_switch_id;
94
95 // vector of queues from the components
96 Vector<Vector<MessageBuffer*> > m_in;
97 Vector<Vector<MessageBuffer*> > m_out;
98 Vector<NetDest> m_routing_table;
99 Vector<LinkOrder> m_link_order;
100 int m_virtual_networks;
101 int m_round_robin_start;
102 int m_wakeups_wo_switch;
103 SimpleNetwork* m_network_ptr;
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86 // vector of queues from the components 87 Vector<Vector<MessageBuffer*> > m_in; 88 Vector<Vector<MessageBuffer*> > m_out; 89 Vector<NetDest> m_routing_table; 90 Vector<LinkOrder> m_link_order; 91 int m_virtual_networks; 92 int m_round_robin_start; 93 int m_wakeups_wo_switch; 94 SimpleNetwork* m_network_ptr; |
95}; 96
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106// Output operator declaration
107std::ostream& operator<<(std::ostream& out, const PerfectSwitch& obj);
108
109// ******************* Definitions *******************
110
111// Output operator definition
112extern inline
113std::ostream& operator<<(std::ostream& out, const PerfectSwitch& obj)
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97inline std::ostream& 98operator<<(std::ostream& out, const PerfectSwitch& obj) |
99{
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115 obj.print(out);
116 out << std::flush;
117 return out;
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100 obj.print(out); 101 out << std::flush; 102 return out; |
103} 104
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120#endif //PerfectSwitch_H
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105#endif // __MEM_RUBY_NETWORK_SIMPLE_PERFECTSWITCH_HH__ |
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